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STM32F103 ADC clock on DocID13587 Rev 17 is right ?

isjeon
Associate II
Posted on October 08, 2016 at 05:10

http://www.st.com/content/ccc/resource/technical/document/datasheet/33/d4/6f/1d/df/0b/4c/6d/CD00161566.pdf/files/CD00161566.pdf/jcr:content/translations/en.CD00161566.pdf

page 12 

3. To have an ADC conversion time of 1 �s, APB2 must be at 14 MHz, 28 MHz or 56 MHz.

Is this right information ?

If APB2 is 40Mhz , adc clock prescale = 2(div 2) and sampling time 7.5 , then Tconv=20 clocks at 40Mhz. (40Mhz / 2 / 20 = 1 Mhz)

In this case, conv time is 1us as well.

Am i missing somethihg ?

Thanks.

#stm32f103-adc-clock
2 REPLIES 2
Posted on October 08, 2016 at 14:51

But you can't clock the ADC at 20 MHz, the converter has a maximum rated speed of 14 MHz, which you can get from 28/2 or 56/4

See fADC on pg 75

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isjeon
Associate II
Posted on October 08, 2016 at 18:33

Thanks.. i understand it.

If so , 1us conversion can be done if the APB2 clock is 14Mhz ?

minimum adc presaler is 2. 

if APB2 = 14Mhz, and ADC clocks = 7 Mhz ,

minimum conversion time = 14 clocks..

500 Ksps is possible 

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