migration from uPSD3200 to STM32

[rs11]

Posted on November 18, 2008 at 20:08

migration from uPSD3200 to STM32

[rs11]

Posted on May 17, 2011 at 12:50Is there any benchmark data that compares the code size and data size of an existing software which migrates from uPSD3200(8032 based) to STM32 (Cortex-M3 based)? I would imagine that the 8-bit,CISC in 8032 to 16/32-bit,RISC in Cortex-M3 should cause the code size to increase (dont know by what % though!). Can someone throw some light here.. I am hopeful that the data size would remain the same since Cortex-M3 boasts of having un-aligned data access built into the hardware, letting the compilers pack all the data in memory. Can someone tell me which compilers does (or does not)take this into account?

[obtronix]

Posted on May 17, 2011 at 12:50

Cortex code size is about 1/4 the size of 8051 code according to

www.iqmagazineonline.com/IQ/IQ16/LowRes.pdfs/Luminary(pg28-32)IQ16.pdf

[st3]

Posted on May 17, 2011 at 12:50

Quote:

On 04-11-2008 at 04:55, Anonymous wrote: Cortex code size is about 1/4 the size of 8051 code according to

http://www.iqmagazineonline.com/IQ/IQ16/LowRes.pdfs/Luminary(pg28-32)IQ16.pdf

All that article actually says is,

Quote:

... ARM reports that Cortex-M3 requires about 1/4th the code space of an 8051.

No reference is given to how ARM arrived at that figure, how generally applicable it is, etc, etc - and, of course, ARM's is hardly an independent view in this matter, is it...?! 😉 The context in the article is,

Quote:

... an 8-bit CISC machine like the 8051 is actually a very inefficient architecture for modern high-level software.

Which is assuming that the 8051 is being used inappropriately - so, if you have a well-optimised, appropriate 8051 application, I guess the comparison will be very different...? So, does anyone have a reference to the original ARM publication that made this ''25%'' claim? [ This message was edited by: st7 on 11-11-2008 18:12 ] [ This message was edited by: st7 on 11-11-2008 18:13 ]

[st3]

Posted on May 17, 2011 at 12:50

Quote:

if you have a well-optimised, appropriate 8051 application, I guess the comparison will be very different...?

The Keil documentation seems to provide a more realistic illustration:

http://www.keil.com/support/man/docs/gs/gs_ma_portaccess.htm

illustrates a case where the 8051 requires only 25% of the code size of a corresponding Cortex program; Whereas

http://www.keil.com/support/man/docs/gs/gs_ma_pointeraccess.htm

illustrates a case where the Cortes requires 25% of the code size of a corresponding 8051 program! Thus, as I suspected, it depends very much on the specific nature of your particular application - and any so-called ''general'' figures you may see must be taken with great caustion!