Cortex-M0 ADC Latency STM32F030

markjohnson9 · ‎2015-12-21

Posted on December 21, 2015 at 17:46

Clarification needed... When does the ADC EOC Flag get set? Before or after the ADC_DR write latency?

ADC clock settings:

Pclk/4 = 40MHz/4=10MHz(ADC_CLK 100nS). Write latency spec: 8.5 fpclk typ. (8.5 * 100ns = 850ns latency).

RM0360 Description pg. 195

The ADC sets the EOC flag in the ADC_ISR register as soon as a new conversion data result is available in the ADC_DR register. An interrupt can be generated if the EOCIE bit is set in the ADC_IER register. The EOC flag is cleared by software either by writing 1 to it, or by reading the ADC_DR register.

#cortex-m0-adc

re.wolff9 · ‎2015-12-21

Posted on December 21, 2015 at 23:21

The idea is that EOC gets set when the DR has become valid. You could be busy-waiting for the result, and thus notice the change as it happens. The whole idea would be void if you then had to wait another 8.5 cycles (of a different clock!) before you can access the result.

In fact, the 8.5 cycles sounds as if that is the time that the ADC takes to calculate the result. Not a ''write delay''.