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STM3F103 Configure CAN FIFO_0 and FIFO_1 to work together

iagenjo
Associate
Posted on April 17, 2015 at 17:00

Dear STM32 support,

I am working with a STM32F103 device.

CAN FIFO_0 is working fine alone.

CAN FIFO_1 is working fine alone.

But when configuring both CAN FIFOs to work together, sit eems that FIFO_1 is not receiving any message.

Both FIFOs have equivalent filters, I mean, filters with different indexes,

but the masking itself are the same for both FIFOs.

Questions are:

1) Is it posible to configure and make work both CAN FIFOs together?

 If yes:

 2.1) Are there any  special tricks to take into account?

 2.2) When configured together, does FIFO_0 has higher priority tan FIFO1?

Thanks a lot for your help.

#can-fifo
3 REPLIES 3
Posted on April 17, 2015 at 17:06

but the masking itself are the same for both FIFOs.

Don't you see that as a problem? Switch the filter indexes,vs FIFO and see if it ALL goes to the other FIFO.

Then configure the filters to discriminate different content, and route it to different FIFOs
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jpeacock
Associate II
Posted on April 17, 2015 at 19:53

The FFA1R CAN register selects either FIFO 0 or FIFO 1 for a filter.  There's no way to select both since it's a single bit.  I don't understand how you can direct messages to both FIFOs?  They will go to one or the other FIFO depending on filter match.

If you want a single message stream then both FIFO interrupts will have to write messages to the same queue set up by your program.  Your CAN protocol listener pulls each message off a single queue, no priority for one FIFO over the other.

Be aware what you are doing is the opposite of how CAN is supposed to work.  The two FIFOs are there for a reason.  The CAN hardware resolves collisions by ensuring higher priority messages are sent first.  High priority messages (emergencies, safety, synchronization, heartbeats) need to be processed as they arrive, not in order, since they are time critical.  One FIFO is dedicated to high priority, the other to standard priority messages (data transfers).  You can still merge messages into a single queue for the protocol listener but high priority arrivals are inserted at the beginning of the queue, standard arrivals at the end.

If you don't have a message queue you can still merge by polling:

set a flag for next FIFO to poll, start at 0

loop: poll FIFO selected by flag

  if data ready, read message, toggle the FIFO polling flag, restart loop

  if no data poll the FIFO not selected by flag

  if second FIFO has data, get message, no change to polling flag

  loop

That way you always poll the other FIFO after receiving a message so each one has equal priority.  This isn't the recommended way for any net stack though, far better to have a message queue feeding a network stack task.

  Jack Peacock
Walid FTITI_O
Senior II
Posted on September 01, 2016 at 17:08

Hi a.m..ismael.001,

It is related to a recent reported bug in Receive function about FiFONumber. It is under fix phase. Meanwhile , add the following line into can_Receive_IT() function before FMI line :

hcan->pRxMsg->FIFONumber = FIFONumber;

Check threads related to this topic:

[DEAD LINK /public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Configure%20CAN%20to%20receive%20in%20both%20FIFOs&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B&currentviews=53]thread1[DEAD LINK /public/STe2ecommunities/mcu/Lists/STM32Java/Flat.aspx?RootFolder=/public/STe2ecommunities/mcu/Lists/STM32Java/%5bSTM32F2%5d%20issue%20with%20CAN-HAL%20interrupt%20receivng&FolderCTID=0x01200200770978C69A1141439FE559EB459D758000F9A0E3A95BA69146A17C2E80209ADC21&currentviews=18]thread2

-Hannibal-