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Reset TIM counter on external signal edge?

TDK
Guru
Posted on January 07, 2016 at 01:53

I'm using a timer in PWM mode to create a clock source.  I'd like to be able to reset that timer so that the TIM edges coincide with an external (asynchronous) source.  If there is no edge on the external source, I still want the timer to continue at its predefined frequency.

Now, obviously there are a few ways to do this.  The easiest is probably using an EXTI interrupt and resetting the counter to 0 on an external clock edge.  However, the external source is pretty high frequency (~3Mhz), so using that method would take up a prohibitive amount of CPU resources.  Is there a way to trigger the timer to reset when the TIM1_ETR pin goes low that doesn't take up CPU cycles?

For example, I'd like the rising edge on 10 to reset the PWM signal on 11 so the edges coincide (within a clock cycle or two).

 0690X00000604yVQAQ.png

From looking in the documentation, it is not clear, but there was enough to suggest it may be possible.

Using a STM32F405 chip and the TIM1 timer, if it matters.

Many thanks,

Tim

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3 REPLIES 3
Posted on January 07, 2016 at 02:03

I guess I'd look at the PWM Input example for inspiration

  /* Select the TIM4 Input Trigger: TI2FP2 */

  TIM_SelectInputTrigger(TIM4, TIM_TS_TI2FP2);

  /* Select the slave Mode: Reset Mode */

  TIM_SelectSlaveMode(TIM4, TIM_SlaveMode_Reset);

  TIM_SelectMasterSlaveMode(TIM4,TIM_MasterSlaveMode_Enable);

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TDK
Guru
Posted on January 07, 2016 at 02:27

Thanks clive1, that does seem like a good place to start.  Will post again if I figure it out.

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TDK
Guru
Posted on January 07, 2016 at 16:05

Okay, I was able to get this working. Some of the relevant code:

TIM_SlaveConfigTypeDef slave_config = {
TIM_SLAVEMODE_RESET, // TIM_Slave_Mode
TIM_TS_ETRF, // TIM_Trigger_Selection
TIM_TRIGGERPOLARITY_NONINVERTED, // TIM_Trigger_Polarity
TIM_TRIGGERPRESCALER_DIV1, // TIM_Trigger_Prescaler
0};
HAL_TIM_SlaveConfigSynchronization(info->handle, &slave_config);

The reset occurs 5 clock cycles after the trigger actually occurs, which I can live with. 0690X00000605HgQAI.png 0690X00000605KFQAY.png
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