STM32F411xx flash latency discrepancy

[russell23]

Posted on April 21, 2015 at 08:32

The reference manaul for the STM32F411 series says that for a CPU running at 100MHz on a 2.7-3.6 supply voltage, the flash latency should be 3 wait cycles. 

However, the CMSIS startup file (system_stm32f4xx.c v1.5.0 dated 06-March-2015) provided with v1.5 of the std periph driver set it to 2 wait cycles:   /* Configure Flash prefetch, Instruction cache, Data cache and wait state */   FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS; But the comments at the top of the file for STM32F411xx series agrees with the reference manual that the latency should be 3WS.  Is this a bug in the CMSIS file or a non-documented optimisation for this processor? Thanks

[waclawek.jan]

Posted on April 22, 2015 at 17:51

Obviously a copy/paste error, taken over from older version where there was no '411 only '401 (for which 2WS is adequate for the max. frequency (which is 84MHz for that one) and high enough power voltage).

OTOH, a deserved punishment for relying on the ''library''... 😉 Pity it's so rare somebody from ST reads this forum. JW