STM32F4xx system clk

[damiano2]

Posted on April 29, 2015 at 10:46

Hi,

I have a doubt concerning the clock architecture of the MCU in subject.Can the System Clock be used directly for any master (CPU core, DMA etc.) without passing through the AHBx prescaler. The reason for this question is to understand if it is possible to have a core running faster than the FMC peripheral.Thanks and regardsDamiano #clock #stm32f4

[waclawek.jan]

Posted on April 29, 2015 at 10:58

> Can the System Clock be used directly for any master (CPU core, DMA etc.) without passing through the AHBx prescaler.

No.

> The reason for this question is to understand if it is possible to have a core running faster than the FMC peripheral.

What's the point? FMC bus timing has many degrees of freedom, see FMC registers. JW

[damiano2]

Posted on April 29, 2015 at 11:08

Thanks for the answer.

It has many degrees of freedom, but in Mode B (to emulate 8080 port to drive a display) the NWE always rise 1HCLK before the end of write transaction.page 1603 of reference manual)If you have a stream of data through DMA the duration of high pulse on NWE is equal to 1 HCLK. If you need to go fast with the CPU clock then this high pulse is too short for the vast majority of displays.Damiano

[waclawek.jan]

Posted on April 29, 2015 at 11:20

Yes, this is a PITA with both FMC and FSMC and has been discussed previously.

https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=https%3a%2f%2fmy.st.com%2fpublic%2fSTe2ecommunities%2fmcu%2fLists%2fcortex_mx_stm32%2fmemory%20with%20long%20write%20recovery%20time%20with%20FSMC%20of%20STM32F407IG&FolderCTID=0x01200200770978C69A1141439FE559EB... Many display controllers err on the safe side and quote a longer hold time than absolutely necessary, but so should you of course. Unfortunately, there's no simple solution to this problem I am aware of. Goes to the feature request list for ST... :( JW