Posted on February 13, 2017 at 23:26It all comes back to ESR.
We need the capacity to supply spikes of current requirements.
spikes come from transistors changing state.
In a ' VLSI ' processor thousands of transistors toggle on an internal clock phase, and another and another just inside one cpu cycle.
So the spikes are aggressive and predictable mostly.
Some spikes are long and deep, some are shallow, so the impedance of requirements changes from phase to phase within a single cpu cycle.
Hence the requirement to have several capacitance values to accommodate the differing current densities Vs frequency response of the capacitors, the efficiency of which comes back to ESR.
The current draw profile determines the capacitance required and is predicable, the engineers have suggested the worst case requirement, however if you project is not so aggressive ( running only a uart for example) then you can get away with less caps.
the symptoms of insufficient capacity are; is inconsistent execution of code that you know works.
its hard enough to debug code, let alone have a hardware issue as well.
Actually on the Oscilloscope, if you can see the 3v3 line drop by 200mV then you are only just ok.
What you cant see on the scope is the rail on the chip die running through really thin wires.
if the voltage drop on the die is 1V you will likely see aberrations of crashing.
This will occur when you have 7 DMAs, 2 CANbus and 14 Serial processes running...
but otherwise you should be ok... mostly.
please check the ripple current of your capacitors, it is important for accommodate the required ESR.
