stm32f373 adc ftrig

othane · ‎2017-10-29

Posted on October 30, 2017 at 05:13

Hi,

Looking at the other stm32 MCU's like the stm32f407 I see in their datasheet a spec fTRIG (aka the External trigger frequency) ... however I cannot see the same spec for the 16bit SDADC on the stm32f373 datasheet ... indeed it is even there for the stm32f373 12 bit ADC.

It seems I can trigger an ADC via the JEXTSEL bits from an EXTI11 line or a TIM TRGO output etc just like for all the other ADC's. What is the max trigger frequency for this please (or did I miss it)?

Thanks

#stm32f373-adc-trigger #stm32f373 #synchronize

S.Ma · ‎2017-10-30

Posted on October 30, 2017 at 08:26

Sigma Delta ADC is an analog IP which is present only in specific STM32 families.

Look at the datasheet and reference manual, then board examples for this SDADC in cube.

othane · ‎2017-10-30

Posted on October 31, 2017 at 00:59

Thanks, but this is not a question of how to do this, I have code to do it (almost).

I am instead looking for a specification for the fTRIG rate on the SDADC so that I know if I trigger the ADC at a rate of say 20kHz or 50kHz etc, and it will work reliably across all the stm32f373 chips I get. I am just about to start testing the code I have to see what I can actually achieve, but a guaranteed spec is really required here (especially since it is a published spec for the other 12 bit ADCs).

That is unless I am miss understanding the design and the chip does not support this feature?

Thanks.

othane · ‎2017-10-31

Posted on November 01, 2017 at 02:41

So i have done some testing by triggering the Injected mode on SDADC1 using TIM19_CH2's rising edge.

The SDADC_CLK is at 6MHz (SYSCLK @72MHz prescaled by 12), JCONT is 0, CR2->FAST is 0 (it seems to be irrelevant anyway), and the CR1->SLOWCK bit is 0.

I find that I get reliable triggering up to about 12kHz, after this I think I am dropping samples from the ADC. To test this I have the TIM19_CH2 mapped to pc11 which I monitor on the scope. Then I have the ADC populating a buffer via a DMA with 100 samples, when I get the DMA complete ISR for all 100 samples I hit a break point and I count the number of edges on pc11 using the scope .... I get 100 edges reliably up to about 12kHz, but after this I start to see many more edges as I believe the ADC cannot service all the triggers.

Since I am converting a single channel I was expecting fTRIG to be closer to at least the 16.66kHz of the fast mode with multiplexed channels (ideally closer to the full 50kHz for the non multiplexed, but I could understand why using an external trigger might make this drop back to multiplexed mode) .... But it seems I am getting a response closer to the 12.5kHz of the one channel slow mode which I was not expecting.

Can anyone confirm the fTRIG spec or tell me how I might increase this sample rate please ?

Thanks.