cancel
Showing results for 
Search instead for 
Did you mean: 

STM32F407 I2S Clocking Problem

lperthel
Associate
Posted on August 18, 2015 at 23:52

Hi All,

I am trying to play a 1.378 kHz triangle wave (32 points sampled at 1kHz) using the embedded CS43L22 audio codec. However, when I probe my headphones with my oscilloscope, the output is a 1.67 kHz wave, which makes me suspect this is a clocking problem. For the I2S sampling I followed Table 126 (page 897 RM0090) and set the following parameters for my clock:

System Clock source | PLL (HSE)
SYSCLK(Hz) | 168000000
HCLK(Hz) | 168000000
AHB Prescaler | 1
APB1 Prescaler | 4
APB2 Prescaler | 2
HSE Frequency(Hz) | 8000000
PLL_M | 8
PLL_N | 336
PLL_P | 2
PLL_Q | 7
PLLI2S_N | 271
PLLI2S_R | 2
I2S input clock(Hz) | 135500000
|
To achieve the following I2S config: |
- Master clock output (MCKO): ON |
- Frame wide : 16bit |
- Audio sampling freq (KHz) : 1 |
- Error % : 0.0183 |
- Prescaler Odd factor (ODD): 0 |
- Linear prescaler (DIV) : 2 |

The part I am unsure about and think might be where my bug lies is configuring the clock control of the codec. All the examples I see online write: WriteRegister(0x05, 0x81); // Clock configuration: Auto detection. Divide I2S_MCK by 2. However, I feel auto-detecting the clock might not be the correct decision for me. The CS43L22's Serial Port Clocking table (page 29 of DS792F2) only shows MCLK frequencies of 288 MHz,288 MHz, 2896MHz, 9344 MHz, 12MHz,24 MHz, and 27MHz. Obviously, none of these coincide with my I2S master output clock of 5 MHz. Do I need to change my PLL values to output one of the clock speeds listed in the CS datasheet? I send the triangle wave using the following:

//saw tooth
uint16_t beep[] ={
0x000,0x100,0x200,0x300,0x400,0x500,0x600,0x700,0x800,0x900,0xA00,0xB00,0xC00,0xD00,0xE00,0xF00,
0xFFF,0xEFF,0xDFF,0xCFF,0xBFF,0xAFF,0x9FF,0x8FF,0x7FF,0x6FF,0x5FF,0x4FF,0x3FF,0x2FF,0x1FF,0x0FF 
};
void play_beep(){
int i;
while(1){
for(i=0;i<32;i++){
while(!(SPI_I2S_GetFlagStatus(SPI3, SPI_I2S_FLAG_TXE)))
;
SPI_I2S_SendData(SPI3, beep[i]);
}
}

Thanks
1 REPLY 1
Posted on August 19, 2015 at 07:43

I2S_MCK does not output at the frequency of PLLI2S; PLLI2S is the input frequency to the I2S module and MCK is divided by factor given by I2SPR register. It may not be quite clear from the description, but MCK is 256*CK. Re-read the ''Clock generation'' sub-chapter of the SPI/I2S chapter, and description of SPI_I2SPR register.

Scope the clocks (master-clock MCK, bit-clock CK, word-select-clock WS(often called LRCK for left-right clock)).

JW