[solved]STM32F7 NOR memory with FMC

[rmszal]

Posted on September 07, 2015 at 11:34

Hello,

I have some problems with FMC when I try to port my code from SMT32F407(with FSMC interface) to new project based on STM32F746(with FMC). The only changes I've made are timings(adapted to 216 MHz clock) and init structures(FSMC => FMC). I have also SRAM connected to the same data and address bus and it works well, so I think that my hardware is ok and problem is inside init code. Thus, I have few questions: is there any difference between using FMC on STM32F4 and STM32F7? Should I change or add something in initialisation code when using FMC on STM32F7? #nor-flash-fmc-stm32f7

[Nesrine M_O]

Posted on September 07, 2015 at 15:04

Hi mszal.rafal,

I'd highly recommend you to have a look to this

http://www.st.com/web/en/resource/technical/document/application_note/DM00164538.pdf

that provides guidelines on hardware migration  from an existing STM32F42xxx/STM32F43xxx device to STM32F74xxx/STM32F75xxx device based design.Also go to the project under STM32Cube F7 package:STM32Cube_FW_F7_V1.1.0\Projects\STM32756G_EVAL\Examples\FMC\FMC_NOR, it can be very useful.-Syrine-

[rmszal]

Posted on September 08, 2015 at 13:24

Thank you for response Syrine.

I've read this application note and I can see no difference between FMC and FSMC when it comes to NOR flash. My init code is strongly based on example from cube package that you've mentioned: http://pastebin.com/DE5qJJhM I've also compared BCR1 and BCR3 registers values on debug and they looks the same on STM32F4 and STM32F7 . Do you have any suggestions what else should I check? Regards, Rafal

[waclawek.jan]

Posted on September 08, 2015 at 13:52

> I have some problems with FMC

What problems exactly? > I have also SRAM connected to the same data and address bus and it works well, I can't see that initialized in your code. Post the relevant GPIO and FMC registers content. JW

[rmszal]

Posted on September 08, 2015 at 15:17

Hello Jan,

I don't use SRAM right now, I've tested it and it works so I comment it out and focused on NOR. I'm just pretty sure that hardware is ok. Here is SRAM init code: http://pastebin.com/8cw9BnXY When I try to read ID I get 0xFFFF. It looks like NOR does not respond. I can see on oscilloscope that chip select signal is generated. FMC registers right after init: http://pasteboard.co/uf0x4Ej.png

[waclawek.jan]

Posted on September 08, 2015 at 16:39

> I don't use SRAM right now, I've tested it and it works so I comment it out

And the chipselect of the SRAM after ''commented it out'' is...? JW

[rmszal]

Posted on September 08, 2015 at 18:45

Chip select of the SRAM (PD7) is configured with the rest of FMC pins as AF push-pull with pull-up and stays high during NOR tests.

[waclawek.jan]

Posted on September 08, 2015 at 19:03

I see.

Humm. So, you say you can see all 3 control signals (chip select, read, write) toggling (as observed directly on the memory's pins to exclude faulty soldering), data changing when writing as expected (you can write dummy data with only one bit cleared at a time to observe proper wiring), yet no response to the ID command? Is this an *identical* board with the '40x board, only with different mcu, or is this a new design? If the latter, couldn't the data or address pins be swapped? It wouldn't matter for the SRAM but it would matter for the FLASH. JW

[rmszal]

Posted on September 10, 2015 at 15:43

Strange, but it finally started to work when I disabled D-Cache. I will write something more when I figure out what exactly happened.

Thank you for help Jan.

[waclawek.jan]

Posted on September 10, 2015 at 16:26

Hummmm.

That sounds like you've been hit by a cache-gotcha ... 😉 Unfortunately, there's no equivalent of PM0214 for the STM 'M7; but if the memory access behaviour is the same as in PM0214 Tab.13, the FMC area lies in ''External RAM'' region, which is of ''Normal'' memory type, thus cacheable, reorderable... JW