Different Sampling Rate for STM32F427IG controller

[nidhi]

Posted on March 15, 2016 at 04:43

Hi,

I

amusing STM32F427IG controller with 

STM32Cube_FW_F4_V1.10.0software. I need to know if I can program different sampling rate for differentchannels of same ADC?

Problem statement: In ADC1 need toscan three channels CH1, CH2 and CH3 all at different sampling rates CH15000SPS, CH2 50000SPS and CH3 1000SPS. Can this be done?

Presently I am able to scan them atsame sampling rate using Timer2 to set sampling rate, and DMA transfer toSDRAM. But would like to know if scanning at different sampling rate possible?If yes then what mode to use and what will be the settings?  

[Tesla DeLorean]

Posted on March 15, 2016 at 05:38

No

You would want to use multiple ADC

[nidhi]

Posted on March 15, 2016 at 06:29

Hi clive1,

You mean to say this kind of setting is not possible and I will have to use different ADC's e.g. ADC1 with one sampling rate, ADC2 with other. Using same ADC will not work. But there is a mode described below which states that different sampling time possible? 1.2 Multichannel (scan), single conversion mode 1.2.1 Description This mode is used to convert some channels successively in independent mode. With the ADC sequencer, you can use this ADC mode to configure any sequence of up to 16 channels successively with different sampling times and in different orders. You can for example carry out the sequence shown in Figure 2. In this way, you do not have to stop the ADC during the conversion process in order to reconfigure the next channel with a different sampling time. This mode saves additional CPU load and heavy software development. ________________ Attachments : Capture.PNG : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006I1HP&d=%2Fa%2F0X0000000bkj%2FIGj0E_s2hBgiK3pYdhR_z5foc1g30dpSbaIyCmIaEQk&asPdf=false

[re.wolff9]

Posted on March 15, 2016 at 08:26

You could set your sampling rate to 50kHz, and then discard 2 out of three samples for the first channel. You wouldn't notice the performance impact of those two ''unnecessary'' DMA transfers. If you then allocate a buffer of 100 samples (50 each), you'll  get an interrupt 1000 times per second, and you can inject the last channel. 

All this would require more efficient programming if you were close to the limits of the hardware. If say you needed to sampel at 1/6MHz, 1/3MHz and 1/2MHz while your ADC can only do 1MHz. All this difficult stuff is not necessary if your problem is exaclty as described because IIRC your MCU has 3 separate ADCs. Another option with the F4 ADC module is to configure a sequence of CH2 CH2 CH2 CH1 to get a 3:1 ratio of CH2 samples to CH1 samples. But now your CH2 sampling is not regular. If that matters to you I don't know. 

[nidhi]

Posted on March 15, 2016 at 08:53

Hi Roger,

Thanks for the suggestionsIn my case can't use the first option as I am doing a DMA transfer to external SDRAM and reading and then discarding will become too messy.The second option that you suggested I am not aware of that mode can you explain that mode a bit more so that I evaluate that as well. Like how to configure a sequence of CH2 CH2 CH2 CH1.

[Tesla DeLorean]

Posted on March 15, 2016 at 10:22

I mean you posed a question and I indicated what you asked seems technicallly outside the realm of what the hardware can naturally do.

Is the sample rate for channel two really 50000 or 5000 sps? The latter might allow for the kind of rank ordering list  of channels. But it is NOT the question you asked.

[nidhi]

Posted on March 16, 2016 at 02:22

Hi Clive,

Yes the sampling rate for CH2 should be 50000SPS.And I need solution to achieve ADC1 scanning three channels CH1,CH2 and CH3 and all at different sampling rates CH1 5000 sps, CH2 50000 sps and CH3 at 1000 sps.

[Tesla DeLorean]

Posted on March 16, 2016 at 02:43

Ok, I'd read 15000 for the first one, but never mind.

The 5:50:1 ratio is NOT going to fit into the 16 channel rank table. The 1:10 ratio does, and you'd have to inject the 3rd channel. I'd attack this by sampling all 3 at 50 KHz, and do a hard coded array decimation at 1 KHz (150 to 56 half-words). If sampling at the same instant is critical (rather than slewed), I'd do it with 3 ADC in Triple mode, into Internal SRAM.