Crystals and load capacitors for stm32l432

[Geoffrey1]

Posted on July 10, 2018 at 14:37

I've been designing sub-gram boards for data logging on songbirds using the stm32l432.  Although mostly I use ultra-low power external RTCs, I recently built a test board using a 4pf 32768 crystal.  The question was then how to determine the load capacitors.  After reading the relevant ST appnote and stm32l432 datasheet I assumed that the pin capacitance was ~5pf and, given the simple board, minimal stray capacitance.  This suggested 3pf load capacitors((4-5/2)*2) and a load error of 1.5pf without capacitors.   With a predicted error of 125ppm/pf, I thought it reasonable to try without any additional capacitors in the hopes of saving board real estate in the final design.  I did include capacitor footprints for my test board.   Upon testing, I found an error > 800ppm which was surprising for two reasons -- it suggested a much larger load error than 1.5pf and also made clear that the formula for predicting error didn't work at these extremes.

To cut to the chase, I found a derivation for a load equation that wasn't just a simple linear equation and used that to compute the correct load capacitors (see attached python code) which is ~5.8pf.   This means the pin capacitance is about 2pf and not the 5pf ST quotes.  I then wondered about the nucleo boards.  In looking at the bom for the stm32l432 nucleo 32, the crystal is 6pf and the load capacitors are 10pf  (6-10/2) = 1pf  -- so 2pf pin capacitance !

Geoffrey

[waclawek.jan]

Posted on July 10, 2018 at 19:54

Thanks for the report/explanation/code.

I am quite inclined that the 5pF/pin figure in the DS is a very rough figure habitually repeated from DS to DS rather than rigorously determined (it's 'typ.' anyway...), especially since that IMO that figure must somewhat depend on the package, too.

The curve you posted is fitted to your finding, and not from manufacturer data, right? I don't believe the 32.768kHz tuning fork crystals are pullable beyond some 200-300ppm, and I'd say that the 800ppm you've seen was some pathologic oscillation, or maybe intermittent oscillation and the oscillator amplifier picking up external noise instead. Have you tried to experiment with different LSE drive levels with the incorrect load capacitors?

sub-gram boards for data logging on songbirds

This sounds very interesting. Can you please post some photos?

JW

[Geoffrey1]

Posted on July 10, 2018 at 21:07

The curve is based upon the crystal parameters.  Only the two 'dots' are based upon measured frequencies.   I used the parameters for the abracon ABS05W.  In particular, the inputs are C0, C1 and the frequency at a 4pf load (32768).  In the report, 0 load error corresponds to a 4pf load.  The locations of the dots are computed from the crystal parameters and the frequency error.   What's especially interesting is I started with no load capacitors and found an error of ~800ppm.  I used the computed C load error to determine the needed capacitors.  The second dot (~10ppm error) is where I ended up with the 5.8pf load caps.

Actually, I ran the board for a day without caps to measure the RTC drift.  I then computed the error, generated RTC divisors and ran it another day.  As it happened, the divisors were spot on and I had only a very nominal drift (less than a second).    I wouldn't want to depend upon long term stability so far from the design point.

Another thing to notice from the graph.  The traditional sensitivity line is pessimistic for positive load error and optimistic for negative error.  If I were starting from scratch, I'd start with load caps a bit on the small side, and use the resulting frequency error to help compute the correct capacitors.  For those who are interested in the derivation of the load curve equations, here's the app note I used:  

https://www.idt.com/document/apn/831-crystal-load-curve

[waclawek.jan]

Posted on July 10, 2018 at 22:50

Thanks for the detailed explanation. Not all crystal manufacturers provide the model parameters (i.e. both capacitances).

I misunderstood the conditions under which you've observed the +800ppm. But still, I've never seen such a deviative yet - as you've described - apparently stable operation. It seems that these mechanically miniscule crystals behave in a significantly different way than the traditional 'legged tubes' 🙂

As soon as the difference is within a few tens of ppm, I'd call the cap tuning done and gone for software compensation - the STM32 RTCs (except of the ancient 'F1s') have implemented a great calibration feature.

Jan

[STOne-32]

Posted on July 11, 2018 at 01:22

Dear Jan, Geoffrey,

This is an interesting discussion.  Indeed when selecting low plating crystal of 4pF CL,  the pullability factor is high and so any deviation of the Cs, etc, will have a big impact on the frequency deviation vs nominal value of 32,768KHz not like 12.5pF.  However these crystals are optimized to save few nA,  which are important for low power applications. and compromise the robustness.

Your Formula is correct and pin capacitance + Cs should be in range of 2pF to 3pF in general, in our datasheet we are providing worst case typical condition of 5pF ( generic to all I/Os). The best way to compute it is empirically based on your PCB and fine tune the RTC outpout on MCO using an universal counter, until you reach the closed frequency of 32.768KHz.  

Please note that the LSE drive level for such crystal should set at Low or Medium Low and try to calibrate it when VDD is ON and VDD is OFF , just operating on VBAT it may varies a bit vs Voltage that may need a compensation as well.

Cheers,

STOne-32.