Question about nested interrupt handling in ARM.

[Vyacheslav Azarov]

Posted on February 06, 2016 at 09:47

Good afternoon for all.

In flat interrupt model of other processors after entering in handler all interrupts will be disabled automatically as normal. For implement nesting you must enable interrupts by himself. The manuals not has explanation about this. How to control this in ARM?Regards. #interrupts #interrupts

[AvaTar]

Posted on February 06, 2016 at 13:16

Have you tried the ARM infocenter website for documentation ?

Like this one:

http://infocenter.arm.com/help/topic/com.arm.doc.dui0553a/DUI0553A_cortex_m4_dgug.pdf

Other Cortex-M vendors include core documentation in their datasheets/manuals, ST leaves the customer on it's own here.

[Radosław]

Posted on February 06, 2016 at 13:20

Hello.

On Cortex-Mx  if you need disable iterrupts  be shour about that. Cortex M have interrupt priority.  In interrupt handler only interrupt with bigger priority can be handled.  Read about NVIC.  See STM programming manuals correct way to disable interrupts is:

__disable_interrupts();

__DSB(); __ISB();

[Vyacheslav Azarov]

Posted on February 06, 2016 at 14:51

Thank you.

I know those CMIS functions and had read about NVIC attentively. This very useful features of preemption. And tail-chain, late-arriving optimization also. I seem to understand this mechanism. This is very good, everything is done automatically. A critical sections as usual, via the __disable_irq() and __enable_irq().

[Radosław]

Posted on February 06, 2016 at 16:59

Look what is write in last post abaut disabling IRQ, this same must ne done in any similar situation in critical sections.

This is becose next intruction can be executed before write to coresponding reg or disabling interrupt will be finished.