Posted on January 26, 2016 at 01:49The datasheet & reference manual are not entirely clear as to when the ADC is functional. From the datasheet (DocID025433 Rev 7), pp.18, Table 5 shows that the ADC is only operational in Run-Mode and Sleep-Mode. However, in the Reference Manual (DocID15965 Rev 13), pp.109, Table 27 shows that in Low-Power Run Mode and Low-Power Sleep Mode that clocks are not affected. Therefore the HSI RC clock is active and the ADC should be functional in all four of these modes, thereby making Table 5 in the datasheet incorrect for the ADC. Am I reading this correctly?
Also, the reference manual states in �12.2 that the ADC clock is derived from HSI and ranges between 16MHz and 4MHz, depending on the selected divisor. I see also that in
�12.3.2 that
the ADC clock is set regardless of the speed of the CPU. Now the datasheet states on page 102, Table 54, that the ADC may operated down to 480kHz. Is it possible to use a clock other than the HSI RC? If so, how do you get to these other clocks? It appears from Table 54 and what I read in the reference manual that the only possible values for the ADC clock is 16MHz, 8MHz and 4MHz and opearting down to 480kHz cannot happen.
#adc #low-power #stm32l151 #a/d
