Posted on March 03, 2016 at 15:36
Hello ST-community,
I am able to setup my external SRAM and access and test (memtest) its memory regions. It works!
However, I do not know if my configurations are correct. It is hard for me to understand the relation between the datasheet of my SRAM and the STM32F4 FMC interface.
SRAM CY7C1051DV33:
http://www.cypress.com/file/42786/download
STM32F4XX:
http://www.st.com/web/en/resource/technical/document/reference_manual/DM00031pdf
Lets start with the timing (Reference page 1591, Table 256 | SRAM Datasheet Page 6):
- Address Setup <-------Address Setup to Write End?
- Address Hold <-------Data Hold from Address Change?
- Data Setup <-------Data Setup to Write End?
- Bus Turn <-------- ?
- Clock divide ratio <-------- ?
- Data latency <----------- ?
- AccessMode <------------- ?
The frequency? of the SRAM is defined by my HCLK divided by the clock divide ratio?
So if my HCLK is 100 MHz and the clock divide is 2 I get 50 Mhz (20 ns). So my STM32F4 latency is always bigger than the latency of the SRAM (max 10 ns). So ever where 1 would be okay?
Thank you in advance for your help!
My NORRAM INIT looks by the way like this:
init.DataAddressMux = FMC_DATA_ADDRESS_MUX_DISABLE;
init.MemoryType = FMC_MEMORY_TYPE_SRAM;
init.MemoryDataWidth = FMC_NORSRAM_MEM_BUS_WIDTH_16;
init.BurstAccessMode = FMC_BURST_ACCESS_MODE_DISABLE;
init.WaitSignalPolarity = FMC_WAIT_SIGNAL_POLARITY_LOW;
init.WrapMode = FMC_WRAP_MODE_DISABLE;
init.WaitSignalActive = FMC_WAIT_TIMING_BEFORE_WS;
init.WriteOperation = FMC_WRITE_OPERATION_ENABLE;
init.WaitSignal = FMC_WAIT_SIGNAL_DISABLE;
init.ExtendedMode = FMC_EXTENDED_MODE_DISABLE;
init.AsynchronousWait = FMC_ASYNCHRONOUS_WAIT_DISABLE;
init.WriteBurst = FMC_WRITE_BURST_DISABLE;
init.ContinuousClock = FMC_CONTINUOUS_CLOCK_SYNC_ASYNC;
#fmc #stm32f4 #sram
