HSI never ready on STM32F4 Discovery

[Alan Chambers]

Posted on March 24, 2016 at 15:33

I'm trying to set up the RTC on the Disco, have read some documentation, and looked at the many examples that are out there. But I fell at the first hurdle:

      RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR,ENABLE);      PWR_BackupAccessCmd(ENABLE);//To enable backup register operation      RCC_LSICmd(ENABLE);      while(RCC_GetFlagStatus(RCC_FLAG_LSIRDY) == RESET);The flag appears never to beoome set. Are some other things meant to happen first? I can see that the LSION bit is set in RCC->CSR, but the LSIRDY bit is never set. How long should this take? I have the feeling I'm missing something really obvious.Thanks.Al

[Walid FTITI_O]

Posted on March 24, 2016 at 15:42

Hi,

To ensure that is not related to the software the you have implemented, try to Run the example in the Library ''PWR consumption''  that you find at this path

Project\STM32F4xx_StdPeriph_Examples\PWR\PWR_CurrentConsumption.

(Select stop mode by uncommenting #define STOP_MODE in  ''stm32f4xx_lp_modes.c'' , after that select LSI as RTC clock source by uncommenting #define RTC_CLOCK_SOURCE_LSI at the top of ''stm32f4xx_lp_modes.c'')

Tell us then if the problem still existing or has gone.

-Hannibal-

[Tesla DeLorean]

Posted on March 24, 2016 at 16:59

No, RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI) would occur later, this currently does seem to be consistent with the other examples, the RTC source gets selected later.

I can't say I've seen this type of failure. Not sure what tool chain, or optimization level is in use, I'd place some delay between enabling the APB clocks, and enabling access, as there is a potential hazard if they occur too quickly.STM32F4xx_DSP_StdPeriph_Lib_V1.x.x\Project\STM32F4xx_StdPeriph_Examples\RTC\RTC_LSI\main.c

[Tesla DeLorean]

Posted on March 24, 2016 at 17:01

The title is distracting LSI not HSI, if the HSI doesn't start, nothing will run.

[waclawek.jan]

Posted on March 24, 2016 at 17:10

IMO you don't need PWR to be enabled to be able to start/stop LSI. It's not in the backup power domain.

I'd simply start the debugger and play with the RCC_CSR.LSION bit and watch how/whether RCC_CSR.LSIRDY bit follows it. Alternatively, I'd go for RCC->CSR = RCC_CSR_LSION; while (!(RCC->CSR & RCC_CSR_LSIRDY)); Starting from that, the path to accuse the ''library'' and/or an idiotic toolchain/IDE is straighforward 😉 JW

[waclawek.jan]

Posted on March 24, 2016 at 17:16

Ah, and

> How long should this take? 40us, see the datasheet. I guess you have waited that long... 😉 JW

[Alan Chambers]

Posted on March 24, 2016 at 17:20

Argh!! Pardon my foolishness. It turned out my project was running in simulation mode rather than STLink. I evidently need stronger coffee. Sorry for the typo is the title, too.

Al