STM32F0 SPI TxFIFO Flush

[Michal Dudka]

Posted on November 10, 2017 at 20:05

Hi,

i've found simple problem with Tx FIFO in SPI in slave mode. Take a model situation from reference manual (STM32F031) 'Figure 281. Slave full-duplex communication'. Imagine situation when master stops communication after 1st byte. Master returns NSS to high, slave stops communication but in TxFIFO still remain 2-3 bytes of data ! 

Figure 281 suggest  that i should disable SPI with end of communication (rising edge of NSS). But it looks like as illegal operation, datasheet says that correct way to disable SPI needs empty FIFO (FTLVL =0). No matter what i do (disable SPI or not) in FIFO still remains data. And if master will begin any further transmission, it will read these old data from TxFIFO.

Is there any legal way how to flush Tx FIFO ? 

Now i am using procedure:

- Reset SPI in RCC- complete init SPI

but it doesnt looks like a legal procedure...

thanks,

Michal

[S.Ma]

Posted on November 10, 2017 at 20:46

Have you tried pe=0 then pe=1 while busy bit = 0?

[Michal Dudka]

Posted on November 10, 2017 at 21:02

Yes. I've added while(BSY==1) loop and disabling SPI when its BSY==0 but data still remains in TxFIFO ...

[Konami]

Posted on November 21, 2017 at 20:49

I'm having this same issue... what's the proper way to avoid old data in FIFO from being sent?

[Dave S]

Posted on May 04, 2018 at 10:28

I am also having this problem, there does not seem to be any way at all to clear the TXFIFO??

[Bernhard1]

As written in the initial posting from Michal:

Now i am using procedure:

- Reset SPI in RCC

- complete init SPI

but it doesnt looks like a legal procedure...

Regarding the question, if this procedure is 'allowed', I found the following in the STM32F334 Reference Manual (RM0364) on page 1017:

To prevent having unread data, ensure that RXFIFO is empty when disabling the SPI, by using the correct disabling procedure, or by initializing all the SPI registers with a software reset via the control of a specific register dedicated to peripheral reset (see the SPIiRST bits in the RCC_APBiRSTR registers).

Even so it's referring to the RX-side, it seems that both, the 'correct disabling procedure' or a 'software reset' are allowed to disable the SPI. And since the software reset also clears the remains in the TX-buffer I'll walk this route too, since I've the same problem as Michal...

Bernhard

[Zheng Liang]

Thanks Bernhard,

Even the procedure looks illegal, but I think it's the properest way to flush TxFIFO.

I faced same problem with you guys, need to discard the residual bits in TxFIFO If the clocks were missing.

In stm32 offical HAL library, it gives a function called "HAL_SPIEx_FlushRxFIFO", but no method to TxFIFO, and I believe they also don't have the best way to flush TxFIFO.

Although it looks tricky, but works.

Zheng