[BUG Report STM32_Cube_L4_1.5.1]SDMMC TX/TR DMA Dont work

Leo_Panda · ‎2016-09-19

Posted on September 19, 2016 at 15:29

if one use sdmmc DMA for Tx AND Rx it will hang in HAL_SD_WriteBlocks_DMA or

in HAL_SD_ReadBlocks_DMA in the modul stm32l4xx_hal_sd.c The reason is the DMA is enable in the first call of one of the routines and is never disabled. By calling the other routine, CCR dont accept any changes because the DMA was enabled. The configuration fails but register are not checked.

I changed HAL_SD_WriteBlocks_DMA and in HAL_SD_ReadBlocks_DMA so, that the DMA is first disabled and reenabled after the configuration. Now it works perfect.

#sdmmc-dma-stm32l4

Walid FTITI_O · ‎2016-10-11

Posted on October 11, 2016 at 11:47

Hi gang,

First of all, the SD specification don't allow simultaneous Tx transfer and RX transfert, they must be sequetially enabled.

So for the DMA used with SD, there is only one direction at a time and not both Tx and Rx. So we should reconfigure the DMA channel/stream before each DMA read or write on SD.

We note that it is not possible to use a DMA channel for each transfer , because once DMAEN bit is set, the channel that has the highest priority will be automatically selected.

-Hannibal-

serafim · ‎2017-01-13

Posted on January 13, 2017 at 10:59

Hi,

I have the same problem. It seems having deeper roots..

If I configure DMA Rx at channel 4 and do not use DMA Tx channel, transmission is OK.

If I (manually or otherwise) set DMA2 channel 5 to Periperal 7 (DMA2->CSELR |= 7 << 16), transmission fails.

I repeat, Channel 4 is configured, channel 5 is NOT configured, but DMA2 CSELR channels 4 and 5 are assigned to SDMMC.

If I use DMA Rx at channel 5 instead of 4 and assign DMA2 CSELR channels 4 and 5 to SDMMC, transmission STILL WORKS.

It seems to me as a hardware bug with the following behavior:

SDMMC, if connected to DMA controller, and with both channels (4 and 5) in CSELR assigned to SDMMC, uses channel 5.

With best regards, Serafim