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STM8L ADC DMA issues

Ricardo Hassan
Associate III
Posted on June 01, 2016 at 20:52

Hi,

    I am running my ADC in continuous mode to sample multiple channels multiple times.  I am using DMA to transfer the data to RAM in circular mode.  I am seeing occasional corruptions of individual samples.  I also seem to miss the DMA transfer complete interrupt occasionally.  I assume this is because I am not handing the peripherals correctly.  Right now I reset the ADON bit in ADC CR1 in the DMA transfer complete interrupt handler, but I wonder if there is a race condition.  It is possible that the ADC might do some more conversions before it actually shuts off?

     There is a statement in the STM8L reference manual that confuses me, in section 14.3.5 Continuous Conversion Mode.  I will cut and paste a snippet:

''In this mode , the ADC does not stop after conversion but continues to the next channel in the selected channel sequence. Conversions continue until the CONT bit and the ADON bits are set and the converted values are transferred through the DMA to the RAM or EEPROM memory buffer.''

    That doesn't seem right.  Could it mean that ''Conversions continue while the CONT bit and ADON bits are set...''?  It seem that the conversion is started by setting those bits, and that resetting them would stop the conversion.  

    Does anyone have any insight into what's going on?

Thanks,

Ricardo

    

#stm8l-adc-dma
1 REPLY 1
jro
Associate III
Posted on June 06, 2016 at 13:21

Hi Ricardo

I've been using this mode and it seems to work OK for me, though I agree the reference manual is probably wrong as you said! 

I've used Continuous mode for repeated readings from one or two channels, and for one-off sets of readings from more channels. I seem to recall getting peculiar results if the DMA buffer size wasn't an integer multiple of the number of selected ADC channels, but this was a bug in my code and everything seemed OK once I'd fixed it. 

It seems the DMA hardware isn't really capable of truly uninterrupted readings, as there's only one address and count register; I guess if the DMA-complete ISR is fast you could re-load and re-start quite quickly, but I don't see any way of doing long-term cycle-accurate continuous ADC readings. Others may well know better than me on this point...

Cheers

Jonathan