Posted on June 19, 2016 at 14:00It seems that the clock frequency for the I2S peripheral assumes another clock source (PCLK1 ??) than it should. When PCLK1 is different from SYSCLK this results in erronous calculations.
In the data sheet of the STM32L100 it is specified as follows:
''Figure 274 presents the communication clock architecture.. The I2SxCLK source is the system clock (provided by the HSI, the HSE or the PLL, and sourcing the AHB clock).''
