Posted on August 24, 2016 at 05:43I have a STM32F401re Nucleo board + Segger.edu J-Link. I am monitoring I2C signals using an Intronix LogicPort serial bus decoder. The development system is Rowley-Crossworks (v3.6.5.2016061400.2836 🙂 for ARM, which seems pretty good for the .edu licen$e.
I'm having a bit of trouble understanding how the alternate function routing works. I have read everything that I can put my eyeballs on and I went back 7 years on the forum reading all the posts re; F4s. I am using the CMSIS GPIO_TypeDef structs/defines and am avoiding library usage to understand things.
On pg 164, of ''STM32F401xD_E_Ref_Man RM0368 rev4'', Table 27 depicts GPIOx_AFRL & GPIOx_AFRH 32bit registers. Then, on page 46, ''STM32F401xD STM32F401xE DS'' (DM00102166.pdf /docID025644 Rev 3), Table 9, are depicted ''Alternate Function Mapping''. How do these two 'things' work together? I see the relationship. My goal is to use I2C1_SCL routed to port/pin PB8 and I2C1_SDA routed to port/pin PB9. What code do I stuff into the two AFR registers to effect that? Or how about routing I2C1_SCL to PB6 & I2C1_SDA to PB9? Is that possible or are we stuck with what-ever happens to be in the AF04 routing group? In any case, somehow thoe four bits in each AF subgroup route the physical pins to the internal peripherals but I have been unable to determine how that works. Is there a truth table for the specific states listed somewhere? Its probably something too stupid simple for my old brain to figure out!!
Any advice is appreciated and thanks in advance,
armor
#alternate-function-mapping #stm32f4
