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ST9 : DIV2 mandatory when using PLL ?

Posted on November 20, 2002 at 13:33

ST9 : DIV2 mandatory when using PLL ?

3 REPLIES 3
Posted on May 17, 2011 at 11:32

Based on the datasheet, it looks like the DIV2 (see MODER register) is required when using a crystal :

''Since the input clock to the Clock Multiplier circuit requires a 50% duty cycle for correct PLL operation, the divide by two circuit should be

enabled when a crystal oscillator is used''

However, how can we reach the ST9 maximum clock speed (24MHz) with a standard crystal ?

The easiest solution would have been to clock the micro with a 4Mhz crystal and remove the DIV2 option.

Does anyone have tried to remove the DIV2 bit ?

Did it work with your design ?

Jojo

sjo
Associate II
Posted on May 17, 2011 at 11:32

I don't actually see a problem doing this, the DIV2 bit is not used in the 92163 USB devices to obtain the correct internal frequency.

Regards

Spencer Oliver

Anglia
romain2399
Associate II
Posted on May 17, 2011 at 11:32

If you do not use the initial divider-by-2 you may increase your PLL jitter ?