Spurious interrupt on ST72F521?

ken_lyons · ‎2002-12-19

Posted on December 19, 2002 at 21:37

ken_lyons · ‎2002-12-19

Posted on December 19, 2002 at 14:22

I'm getting a spurious interrupt on the ST72F521. Soon after reset, I am setting bit 3 of the port A option register; which configures that pin as an input with interrupt. However, the ei0 interrupt is disabled (bits 4 and 5 of ISPR0 are set to one). Regardless of that fact, when interrupts are enabled with the RIM instruction, the processor seems to take an interrupt at ei0. I haven't done more detailed testing to see if that is the case, but there is anecdotal evidence. Is this expected behavior? If both bits are high in the ISPRx register (level 3), does this really mean that the interrupt is disabled, as the data sheet seems to indicate?

maxime2399 · ‎2002-12-19

Posted on December 19, 2002 at 21:37

I think what you are seeing is normal.

Bits 4 & 5 in ISPR0 are not here to disable the interrupt but to set the interrupt level of ei0 interrupt to level 3.

As long as CC bits I0 I1 are at 11, the running level of the core is 3 and no interrupt is allowed (as no higher running level available, only TLI, TRAP and RESET are allowed).

But when you execute the RIM instruction, the bit I0 of CC is reset, the run level is now 2 and interrupts that are set for level 3 can occur.

If an interrupt has been generated on your port A since it has been initialised as input with interrupt, the event has been latched and the interrupt routine execution should start right after the RIM instruction.

In order to obtain the result you are expecting while using the concurrent interrupt mode only (in concurrent mode, the running level is always 2 or 3), you should set Bits 4 & 5 in ISPR0 to 00 or to 01 in order to disable this interrupt only.

Be carefull, because in case the event occurs it will be latched and the interrupt routine will be executed as soon as you change the configuration of CC or ISPR0...