Posted on January 30, 2003 at 14:40Thanks. Do you know the maximum transfer rate on it for an HCLK of 100 MHz? The timing diagrams for the local bus don't seem to indicate how long you wait after the cycle is complete to when another cycle starts, so I assume that they can be run back to back with no delay. Having very high throughput is required because we will be doing PIO and I don't want that my 1.7MBytes/sec too consume too many processor cycles.
My current calculations:
From the timing diagrams for localbus IO reads, I see that the cycle takes 16T or 160
mailto:ns@100MHz
. So I assume that if could use a REP INSW command and have 60 nsec SDRAM write cycles, then we should be able to do a read from local bus IO, write to SDRAM sequence in something like 160 ns + 60 ns = 220 ns. Does this seem reasonable?
