ST7Lite 09 PWM

[brian4]

Posted on March 02, 2004 at 01:31

ST7Lite 09 PWM

[brian4]

Posted on February 27, 2004 at 06:50

Hi just started using a ST7FLite09.

Cant seem to get the PWM output working in assembler, can anybody let me have a example ASM file so I can check that I have all the correct registers enabled. Many thanks

[dix]

Posted on February 27, 2004 at 07:45

Hi Brian,

I'm not using the same chip, but all ST7 devices use the same assembler code. At init, stage you need to set-up the; ATRH, ATRL regsiters and define the basic frequency. ld A, #$0F ld ATRH, A ; set the upper nibble offset of the AT2 timer. ld A, #$38 ld ATRL, A ; set the lower nibble offset of the AT2 timer. Then set-up the first DCR setting for your PWM duty cycle. This examle shows both PWM1 and PWM0 outputs. ld A, #$0F ld DCR1H, A ld A, #$4A ld DCR1L, A ; set PWM1 initial duty cycle to 9% ld A, #$0F ld DCR0H, A ld A, #$9C ld DCR0L, A ; set PWM0 initial duty cycle to 50% Then you need to enable the actual port outputs. ld A, #$05 ld PWMCR, A ; enable PWM0 and PWM1 outputs. In my system I inverter PWM1, but you probably don't need this bit. bset PWM1CSR, #1 ; invert PWM1 I'm not using the interrupts, so they're disabled here. They should be disabled by default, but I had problems with my chip. bres ATCSR, #5 ; disable the IC interrupt. bres ATCSR, #1 ; disable the OVF interrupt. bres ATCSR, #0 ; disable the CMP interrupt. Next you need to select your clock source. I'm using the CPU clock. bres ATCSR, #3 ; CK0: bset ATCSR, #4 ; CK1: select AT2 clock frequency = CPU clock. Note there is a trick here. When the MCU boots-up, the TRAN bit of the TRANCR register is set. So the first PWM (DCR) setting is correctly adopted. However when you write to the DCR reg. the TRAN bit is automatically cleared. So you have to manage with TRAN bit in software before each write. bset TRANCR, #0 ; enable DCR value transfer. ld DCR1L, A ; set the lower DCR duty cycle. Note you don't have to modify both DCR1H and DCR1L together. If you're making fine adjustments to the duty cycle then you can just modify DCR1L. Regards Steve.

[brian4]

Posted on February 27, 2004 at 08:01

Thanks there is some other registers

This is what I have, seems to be similar but still not working .setuptimer ;Lite Timer Ctrl / Status Reg LTCSR ; Bits 76543210 ; Description:- 00000000 ; |||||||| ; |||||||`---- Bit 0 WDGD (Watchdog Reset Delay) ; ||||||`----- Bit 1 WDGE (Watchdog Enable) ; |||||`------ Bit 2 WDGRF (Force Reset / Reset Status Flag ; ||||`------- Bit 3 TBF (Timebase Interrupt Flag) ; |||`-------- Bit 4 TBIE (Timebase Interrupt Enable) ; ||`--------- Bit 5 TB (Timebase Periode Selection) ; |`---------- Bit 6 ICF (Input Capture Flag) ; `----------- Bit 7 ICIE (Interrupt Enable) ; ; Bits 76543210 ld A,#%00000000 ;Set val to load into LTCSR register ld LTCSR,A ;Lite Time Input Capture Reg LTICR ; Read only register ; ;Timer Control Status Register ATCSR ; Bits 76543210 ; Description:- 00000000 ; |||||||| ; |||||||`---- Bit 0 CMPIE (Compare Interrupt Enable) ; ||||||`----- Bit 1 OVFIE (Overflow Interrupt Enable) ; |||||`------ Bit 2 OVF (Overflow Flag) ; ||||`------- Bit 3 CK (Counter Clock Select CK0) ; |||`-------- Bit 4 CK (Counter Clock Select CK1) ; ||`--------- Bit 5 Reserved ; |`---------- Bit 6 Reserved ; `----------- Bit 7 Reserved ; ; Bits 76543210 ld A,#%00001000 ;Set val to load into ATCSR register ld ATCSR,A ;PWM0 Control / Status Register PWM0CSR ; Bits 76543210 ; Description:- 00000000 ; |||||||| ; |||||||`---- Bit 0 CMPFO (PWM0 Compare Flag) ; ||||||`----- Bit 1 OP0 (PWMO Output Polarity O Not Inv, 1 Inv) ; |||||`------ Bit 2 Reserved ; ||||`------- Bit 3 Reserved ; |||`-------- Bit 4 Reserved ; ||`--------- Bit 5 Reserved ; |`---------- Bit 6 Reserved ; `----------- Bit 7 Reserved ; ; Bits 76543210 ld A,#%00000000 ;Set val to load into PWM0CSR register ld PWM0CSR,A ;PWM Output Control Register PWMCR ; Bits 76543210 ; Description:- xxxxxxx0 ; |||||||| ; |||||||`---- Bit 0 OE0 (PWM0 Output Enable, 1=Enabled 0=Normal I/O Pin) ; ||||||`----- Bit 1 Reserved (Keep Clear) ; |||||`------ Bit 2 Reserved (Keep Clear) ; ||||`------- Bit 3 Reserved (Keep Clear) ; |||`-------- Bit 4 Reserved (Keep Clear) ; ||`--------- Bit 5 Reserved (Keep Clear) ; |`---------- Bit 6 Reserved (Keep Clear) ; `----------- Bit 7 Reserved (Keep Clear) ; ; Bits 76543210 ld A,#%00000001 ;Set val to load into PWMCR register ld PWMCR,A ld A,#01 ld ATRH,A ld A,#50 ld ATRL,A ld A,#05 ld DCR0H,A ld A,#50 ld DCR0L,A ret

[dix]

Posted on February 27, 2004 at 10:34

Hi Brian,

There are two different peripheral timers on the 7Lite09 chip; Lite Time (LT) and the Auto-reload Timer (AT). Unless you're using the Lite Timer as well you shouldn't have to set-up the LTCSR or LTICR registers. The PWM uses the AT timer and the associated registers only. You seem to have disabled the AT timer clock. If you look bits 3 & 4 of the ATCSR you will see that they're CK1 and CK0. These two bits select the clock source. With both bits clear (logic zero) then the clock is OFF. Its normal to use the CPU clock as your source, (i.e. CK1=1 and CK0 =0). I'm not sure you can write to registers with ''reserved bits'' using; ld A, #data ld reg, A. Its probably better to set each required bit via the BSET command. Try setting the clock bit CK1 and let me know if this works. Regards Steve.

[brian4]

Posted on March 01, 2004 at 06:59

Now have it working, it was the CK0 & 1.

Many thanks for your help. Confused on what method to use to write to the Reg. The data sheet shows reserved bits set to zero on a reset, hence the way I have done it Is the BSET & BRES the better method?

[dix]

Posted on March 01, 2004 at 13:06

Hi Brian,

I found a bug in my own code when using ld A, #data That’s why I switched to using the BSET instruction. It slightly safer, because you never write to the ''reserved bits'' of the control reg. Nevertheless if you are using a simple routine to set-up the AT timer, then it should work okay. Don't worry about this too much, as its not a major issue. If your code works then its fine the way it is. Regards Steve [ This message was edited by: Steveboy on 01-03-2004 17:38 ]

[jatin]

Posted on March 02, 2004 at 01:31

Avoid using BSET and BRES instructions when using it with I/O's with mixed configurations(some I/O's in I/P mode and some in O/P mode). For more info, check it in the ST7 Knowledgebase.