st7lite0 PWM question?!!

[huaer2000]

Posted on October 09, 2004 at 03:45

st7lite0 PWM question?!!

[huaer2000]

Posted on May 24, 2004 at 07:50

I write a program like below:

CLR PADR LD A,#$0F LD PADDR,A LD A,#$FF LD PAOR,A CLR PBDR LD A,#0 ;#$7 LD PBDDR,A LD A,#0 ;#$7 LD PBOR,A LD A,#$0C LD ATRH,A LD A,#$0E0 LD ATRL,A ;PWM frequ0K LD A,#2 LD PWM0CSR,A LD A,#$10 ;fcpu= 8MHZ LD ATCSR,A BSET PWMCR,#0 ;Enable loop: LD A,#$0F LD DUTY_H,A LD DUTY_L,A LD A,DUTY_H LD DCR0H,A LD A,DUTY_L LD DCR0L,A JRA loop The problem is the PWM output frequency in the oscilliscope is not stable, it change between 9.8K and 4.9K. I don't know why. could anyone help me to explain it. Best Regards, mcuinterest

[jatin]

Posted on May 26, 2004 at 12:54

It is not the normal behavior. Your code seems to be ok. Pls check your cpu clock on MCO pin and internal RC oscillator settings.

[huaer2000]

Posted on September 20, 2004 at 03:41

I have checked clock the MCO pin and internal RC oscillator settings, there is no problem. what wrong lite0x bug?

mcuinterest

[wolfgang2399]

Posted on September 20, 2004 at 06:04

Perhaps the problem occures because you refresh your Duty Cycle Register in a permanently active loop.

Please notice the text below of the datasheet in the chapter of the Autoreload Timer: Caution: As soon as the DCR0H is written, the compare function is disabled and will start only when the DCR0L value is written. If the DCR0H write occurs just before the compare event, the signal on the PWM output may not be set to a low level. In this case, the DCRx register should be updated just after an OVF event. If the DCR and ATR values are close, then the DCRx register shouldbe updated just before an OVF event, in order not to miss a compare event and to have the right signal applied on the PWM output.Hope it helps WoRo

[sjo]

Posted on September 20, 2004 at 07:09

In your code you are constantly writing to the DCR0 register, this only has to be done once for setup and then only if you need to change duty cycle.

This could cause a problem as the compare is frozen when the DCR0H is written as mentioned above. Regards sjo

[huaer2000]

Posted on October 09, 2004 at 03:45

Dear sir,

you are right, now I update the duty cyle in the overflow interrupt subroutine of auto reload timer. but the problem(PWM output wave form is not very stable) still exists in some duty cyle point(8%-12% around). I don't know why I guess it is because the DCR and ATR are very close. Just like the suggestion in the datasheet, the DCRx register shouldbe updated just before an OVF event, in order not to miss a compare event and to have the right signal applied on the PWM output. But I don't know how to update the DCR value befor OVF envent. can anyone help me!. Best Regards, mcuinterest