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ST72213R PWMART

dave_festing
Associate II
Posted on July 24, 2005 at 08:37

ST72213R PWMART

9 REPLIES 9
dave_festing
Associate II
Posted on July 13, 2005 at 10:11

The PWMDCRx Duty cycle register ''appears'' to have a reset value of 0xFC like the ACLR and CLR registers in the 16 bit timer.

I have to add 5 to the value that I plug into the PWMDCRx register to get my duty cycle times correct.

The manual states that this register is reset to 0x00.

Or is there a minimum value for ''the second edge location of the PWM signal''?

Thanks,

DaveF

wolfgang2399
Associate II
Posted on July 15, 2005 at 07:50

Whoops: Do you relly mean ST72213? There is no PWMDCRx in the ST72213?

And the counter register really is reset to FFFCh at - just like the counter register of the ST72321.

Noted in the datasheet of the ST72213 at chapter 5.3.3.6

and in the datasheet of the ST72321 at chapter 10.4.3.6.

Regards

WoRo

dave_festing
Associate II
Posted on July 18, 2005 at 08:54

Yes, whoops. I do mean the ST72F321.

Chapter 10.4.3.6 talks about using the 16 bit timer in PWM mode. I don't see any reference to the PWMDCRx register here.

I am using the PWMART Chapter 10.3.2 which I am assuming is a seperate peripheral.

I could be missing something important here as I have just started using this part.

Cheers,

DaveF

wolfgang2399
Associate II
Posted on July 18, 2005 at 10:49

Hi DaveF,

sorry, my fault with the timers.

But then what do you mean with the ''reset value of the PWMDCRx''? In my opinion the reset value of the AutoReloadTimer has to be established with the ARTARR.

Which values are you setting to the ARTARR and the PWMDCRx to get what a duty cycle?

Regards

WoRo

dave_festing
Associate II
Posted on July 21, 2005 at 09:48

WoRo,

On page 66 of the manual.

DUTY CYCLE REGISTERS (PWMDCRx)

Read/Write

Reset Value: 0000 0000 (00h)

However, I find that I need to add 5 to the duty cycle value that I put into the PWMDCRx register if I want to get the correct duty cycle.

The ARTARR register sets the ''first edge location'', in my case:

***

#define AUTO_RELOAD_TIME 6 /* Fpwm = Fcounter / 256 - ARTARR */

/* for a Fcounter of 1MHz and ARTARR = 6 you get a 4kHz PWM */

void timebase_PWMART_init(void)

{

ARTARR = AUTO_RELOAD_TIME;

***

Basically I am trying to emulate a classical PWM that uses a triangle waveform generator and a comparator. I have worked out that all I need to do is take samples of my audio waveform using the ADC at 4kHz rate and by using 2 PWM channels, one to generate an ''ON'' period and the other to generate an ''ON plus OFF'' period and NANDing these 2 outputs I can get a centre aligned duty cycle that is related to the amplitude of the incoming audio signal. Here is the ISR that is triggered by the PWM. The PWMDCR1 and PWMDCR2 values are loaded into the PWM and at the next interrupt become the new vlaues for the next duty cycle.

***

@interrupt void timebase_PWMART_ISR(void)

{

uint8_t adc_data_value = 0;

uint8_t off_time = 0;

uint8_t on_time = 0;

mask_interrupts();

if(ARTCSR)

{} // just a read to clear the OVF flag

adc_data_value = adc_read(ADC_CHANNEL_ZERO); // takes about 8uS

off_time = (uint8_t)((adc_data_value) / 2);

PWMDCR1 = (uint8_t)(off_time + 5);

PWMDCR2 = (uint8_t)(250 - off_time + 5);

unmask_interrupts();

}

***

Also, because the PWMDCRx registers need this 5 added to them you can only go to 250, i.e. if off_time was zero then PWMDCR2 gets loaded with 255.

Notes:

- there may be a small issue with taking a 8bit ADC value and dividing it by two, so some samples could be out by 0.5.

- uint8_t is my type for an unsigned 8bit variable.

- would be nice if the ADC had an interrupt flag, but fortunately this is the only job this uP is doing!

The fact that the above works suggests to me that the PWMDCRx register is reset to 0xFC and not 0x00.

Cheers,DaveF

wolfgang2399
Associate II
Posted on July 21, 2005 at 14:58

Hi DaveF,

perhaps I don't understand your program. But as I see the PWM function it works with the AutoReload Counter which will be reloaded with the value of the ARTARR when reaching FFh.

The Reset Value of this register defines the value after a Reset of the µC.

Page 66:

A PWMDCRx register is associated with the OCRx

 

register of each PWM channel to determine the

 

second edge location of the PWM signal (the first

 

edge location is common to all channels and given

 

by the ARTARR register). These PWMDCR registers

 

allow the duty cycle to be set independently

 

for each PWM channel.

As I am reading it the PWM signal will be set at the event when the counter reaches FFh. At the same time the counter will be reloaded with the ARTARR value (first PWM edge).

When the counter value is reaching the OCRx (=PWMDCRx) value the PWM output is going to the opposite state (second edge). Then reaching FFh, realoading the counter and so on and so on.

When you are setting ARTARR to 6 then you will force the counter to run from 6 to 255. Each time reaching FFh it will be reloaded with ARTARR=6.

Best to see on page 62.

Hope it helps

WoRo

dave_festing
Associate II
Posted on July 22, 2005 at 08:19

WoRo,

First off, I agree with and/or understand all of your latest comments.

My main problem is why do I have to put more than 5 into the PWMDCRx register (in my example) to start getting pulses out of the PWM?

page 62

***

The PWM signals all have the same frequency

which is controlled by the counter period and the

ARTARR register value.

fPWM = fCOUNTER / (256 - ARTARR)

***

This tells me that the value in the ARTARR register sets the frequency or pulse repetition rate of the PWM signal. My understanding is that it has nothing to do the actual duty cycle.

Maybe, there is some connection beteen the ARTARR value and the values you can put into the PWMDCRx register but this is not clear to me.

Where the manual states: (the first edge location is common to all channels and given by the ARTARR register). I think what they mean is that ''the first edge location'' AND how often it occurs determines the PWM frequency.

Thanks for continuing with the discussion.

Cheers,

DaveF

wolfgang2399
Associate II
Posted on July 22, 2005 at 10:54

DaveF,

I think you can solve your problem very easily if you know how the whole PWM generation depends on the ART COUNTER.

As the COUNTER of AutoReload Timer will be reloaded with the value of the ARTARR when it exceeds the 255, the counter never will get any value below ARTARR. It counts from ARTARR to 255 reload with ARTARR and counts again...

To generate the PWM signal, the PWM output seams to be switched depending on the result of the comparison of the COUNTER with the PWMDCRx value (= internal OCRx). If ''COUNTER > PWMDCRx'' the PWM output is set to the first state (high or low). else the output is switched to the opposite state (low or high).

The COUNTER will take values from ARTARR to 255. With a PWMDCRx value less than the one of the ARTARR the timer never can generate a real PWM signal.

Please have a look at the figures 39 and 40 on page 62.

Additional the timing:

- the first segment (high or low at PWM output) appeares when ''COUNTER=ARTARR'' until ''COUNTER=PWMDCRx+1''. The length of this segment will be [PWMDCRx+1-ARTARR],

- The second segment (low or high) apeares at ''COUNTER=PWMDCRx+1'' until ''COUNTER = 255+1''. The length of this segment then is [255-PWMDCRx]

... and the complete cycle follows from

[PWMDCRx+1 - ARTARR] + [255 - PWMDCRx] = 256 - ARTARR

Sorry for the lengthy explanation just to say that the PWMDCRx has to be greater or equal to ARTARR. In your aplication ARTARR is 6, which causes ''to put more than 5 into the PWMDCRx register'' for a PWM signal.

Regards

WoRo

dave_festing
Associate II
Posted on July 24, 2005 at 08:37

WoRo,

Thank you for the detailed explanation. I think I finally understand what is happening now 🙂

***

I think you can solve your problem very easily if you know how the whole PWM generation depends on the ART COUNTER.

***

How true! This was my first time using a PWM on any uP. I decided I wanted to go up 62.5KHz for the PWM so choose ARTARR of 6. I realised that I was going to lose some resolution, but didn't connect the very close realtionship between the two registers.

Two guys, at work, who work with the ST7 could not tell me why the 16bit timer CLR register gets reset to 0xFC so I incorrectly jumped to the conclusion the same thing might be happening on the PWMDCRx register.

Thanks again for putting me straight, I really appreciate you sticking with this question to a successful conclusion!

Kind regards,

DaveF