using AutoReload Timer at ST7LITE2X

[wolfgang2399]

Posted on June 02, 2004 at 06:36

using AutoReload Timer at ST7LITE2X

[wolfgang2399]

Posted on May 27, 2004 at 12:37

I have several problems using the Autoreload Timer of the ST7LITE29.

(Using the manual Rev. 2.01 December 2003) 1st: I think the Figure 37 (PWM Signal) is wrong in the line DCRx=FFEh. I took the Figure 35 in the manual of the LITE0 which seems to be correct. Additionally the unknown term MOD00 is called OE0 there. 2nd: In the Timer Control Status Register the description of the Counter Clock Selection (CK[1:0]) says: ... The change becomes effective after an overflow. My question: If I select (counter) OFF (00), when exactly will appeare the next overflow i.e. to reactivate the counter?? Nevertheless the reset value is 00 and sometimes (!???) I can start the counter!! 3rd: To write the Autoreload Register (ATR) the µC does it in two steps - first writing ATRL then ATRH or vice versa (depending on the X-Compiler). Anyway there can be an OVF when your µC just has written one of two bytes. In this case the one byte is loaded to the upcounter with the correct value but the other byte loaded to the counter still holds the old value. This brings a lot of problems to me, because I have to change values in the range of E80h to F40h continuosly and I must not have a crack. Thanks for helping. WoRO

[anshul]

Posted on June 01, 2004 at 08:29

1. The figure 37 in the Lite2 datasheet is correct. The Timer behavior in this device is as follows

PWM goes low when CNTR = DCR+1 and PWM is set when CNTR = ATR+1 The behavior of this ART Timer is different from the Lite0 ART Timer. Yes you are right; the term MOD00 is OE0 in Fig 37. 2. There is a mistake in the datasheet which will be corrected regarding this point. The CK[1:0] bits do not become effective after overflow. They become effective as soon as you write them. 3. This situation will never arise if you first write your ATR value and then enable the timer by selecting the clock.

[wolfgang2399]

Posted on June 01, 2004 at 11:26

Hi Ansh,

thanks for your answer. It solves a lot but not all my questions. As I think the description in the datasheet is a little poor, I need some further hints. - There is a Note on page 56: ''... lower than the DCR value which must be 4095 in this case''. I suppose your explanation ''PWM goes low when CNTR = DCR+1'' meens: ''... at the end of the state CNTR = DCR'' because in my opinion CNTR never meets 4095+1. - when are the bits OVF and ICF really set? With CNTR = DCR or DCR+1 ? resp. ATR/ATR+1. - when is the value of the DCRx register transferred to the shadow register? I found at the description of the flag TRAN : ''... after the next overflow event''. What does that mean at least? If you have any influence with the new revision of the ARTimer description please help them to do it well!! - Notice that the figure 36 is not correct if I take your description of the PWM signal. - Figure 35: Have a look at the pointer from the DFF to the inverter. And what meens counter overflow in this diagram (CNTR=FFDh or CNTR=ATR in respect of a DFF triggered on a negative edge)? Thank you for helping WoRo

[anshul]

Posted on June 01, 2004 at 13:44

You are right, what I meant by PWM goes low at CNTR=DCR+1 is that the PWM goes low at the end of state of CNTR=DCR.

It is for this reason in figure 36 its shown that PWM goes low at DCR, because in this figure the clock is not shown. In the next figure, fig. 37 the change per counter update is shown. The OVF bit gets set when the counter overflows i.e. its value changes from FFFh to ATR value. The ICF bit gets set when an Input Capture occurs, i.e. a seleted edge is detected on the LTIC pin. The DCR preloaded values are tranfered to the DCR shadow register on the next overflow if the TRAN bit is set. The working is as follows when you write to the DCR register then it actually gets transferred to the DCR shadow regsiter when the counter overflow occurs i.e. a conter transition takes place from FFFh to ATR and for this tranfer to take place the TRAN bit should be set, otherwise the DCR shawdow register will not be updated. I hope you have the answers to all your questions.

[wolfgang2399]

Posted on June 01, 2004 at 13:59

Thanks a lot.

A little mistake: I didn't mean ICF but CMPFx (thinking of OCF). In figure 36 you can see that the PWM goes up on overflow but not on CNTR = ATR+1. That's what I mean. The way PWM goes down is quite right. Thanks again WoRo

[anshul]

Posted on June 02, 2004 at 06:36

CMPFx bit gets set when counter matches the value in DCRx register.

PWM goes high when CNTR=ATR+1, the end state of counter = ATR the same way as it goes low.