ST7FLITE10 MCU hanged while the vdd (5V) sudedently drop to ~1V.

alanlai1 · ‎2005-01-09

Posted on January 10, 2005 at 04:43

alanlai1 · ‎2005-01-03

Posted on January 03, 2005 at 22:53

Vdd for MCU = 5V, Set LVD = 4.1V

In the testing, we repeatly to tune the vdd down to 1V, and return to 5V.

Assume when the Vdd drop under 4.1V and rise over 4.1V again, the MCU will be reset.

But the MCU cannot be reset (no clock out again) in our repeatly testing.

Is it any limited rising time / falling time for the Vdd?

alanlai1 · ‎2005-01-03

Posted on January 04, 2005 at 00:01

I checked the page 94 of Lite1 datasheet, please give me some comment. Thank you

In Lite1 datasheet Page 94.

Note: The Vdd rise time rate condition is needed to insure a correct device power-on and LVD reset.

When the Vdd slope is outside these values, the LVD may not ensure a poper reset of the MCU.

1) Is it means that the Vdd cannot connect a cap too large?

But I am using 7805 regulator, the Vout must have some cap, will the cap effect the Vdd risgin time? (Because Transient), how to choice? not use the cap?

2) I search ''LVD Reset'', read some old post, old post said that need to add 0.01uF between RST and GND. What is it for? Please teach me more, thanks a lot.

jatin · ‎2005-01-09

Posted on January 10, 2005 at 04:43

Pls also check if you are using the reset circuit mentioned on page111/131 (with LVD enabled). Pull up resistor must be removed with LVD enabled.