Port 0 Input Specifications

[jdaniel]

Posted on November 18, 2003 at 15:01

Port 0 Input Specifications

[jdaniel]

Posted on May 17, 2011 at 11:56

I'm trying to determine the input voltage requirements (Vih and Vil) for Port 0 on the uPSD3254A. The specification doesn't seem to be listed in table 111 in the user's guide. Should I assume that these specifications match those of the other ports tagged as ''CMOS compatible'' in the port structure descriptions? Or should I assume that they have the same characteristics as the 8032? Better yet, is there an errata sheet indicating these values? Any help would be greatly appreciated.

Best Regards, pHaze426

[joseph2399]

Posted on May 17, 2011 at 11:56

Port 0 and Port 2 are internal address and data bus and can not be used as GPIO. You can assume that this internal address/data bus exhibit the same characteristics as a standard 8032.

[jdaniel]

Posted on May 17, 2011 at 11:56

Moderator,

I think once again I somehow mixed up my explanation. I am confident that the uPSD can drive the address and data signals TO the DPRAM. This is because I am GIVEN Voh and Vol for the uPSD. What I don't know is if the DPRAM can drive data BACK to the uPSD when it's requested. For that, I need to know Vih and Vil of the uPSD and make sure that they are appropriate for the corresponding Voh and Vol of the DPRAM. So: Will TTL-levels reliably drive the inputs of the uPSD? That is, will a 2.4V signal from the DPRAM be interpreted as a hi, or do I need the 0.7Vcc required by all the other MCU ports? Sorry to belabor this point, but the devil's in the details, so to speak. Best Regards, pHaz426

[jdaniel]

Posted on May 17, 2011 at 11:56

Moderator,

Thanks. I understand that these ports cannot be used for GPIO, but these levels are nonetheless important for interfacing to external memory. I'm trying to interface to a Cypress CY7C136 DPRAM and I need to determine if I have to pull up the bus or add any interface logic for the lines. Assuming I used values for a standard intel 8032, which particular flavor would be appropriate? The values for the 8032AH are as follows for port 0: - Vil = 0.7Vmax - Vih = 2.1Vmin - Vol = 0.45Vmax (at 3.2mA) - Voh = 2.4Vmin (at -400uA) The values for the 80C32 are as follows for port 0: - Vil = 0.2Vcc - 0.1V max - Vih = 0.2Vcc + 0.9V min - Vol = 0.3V max (at 200uA) - Voh = Vcc - 0.3V (at -200uA) Do either of these sets of data match up with what I should expect from the uPSD? I ask this only because the values for the uPSD bus that ARE given in the datasheet are as follows: - Vol = 0.45Vmax (at 3.2mA) - Voh = 2.4Vmin (at -800uA) These seem to match up with the bus values for the 8032AH (with a bit more current sourcing capacity). HOWEVER, in figure 17 on page 48, the port 0 structure is described as ''CMOS compatible interface.'' I would normally consider the values listed for the 8032AH as TTL compatible. This makes a big difference in my application as I need to know whether the Cypress DPRAM is capable of reliably driving this bus. Please clarify a bit further if you can. Best Regards, pHaze426

[joseph2399]

Posted on May 17, 2011 at 11:56

Yes you are correct, uPSD operates like 8032AH. It is compatible with both TTL and CMOS interface. If Vol = 0.45Vmax (at 3.2mA) and

Voh = 2.4Vmin (at -800uA) meets the requirement of Cypress CY7C136 DPRAM, then there should be no problem with it driving this bus.