16-bit timer on 561

pete3 · ‎2004-09-01

Posted on September 01, 2004 at 12:57

16-bit timer on 561

pete3 · ‎2004-08-31

Posted on August 31, 2004 at 09:04

Hi all,

I'm using the 16-bit timer on the 72F561 and it's working fine. However the datasheet mentions that the timer is started when a value is written to the CLR (Counter Low Byte) register after an access to the CSR (Control/Status Register). This is stated on p92 of the datasheet. I was wondering if there is a time or other limit to how long can pass between these accesses?

Additionally I am trying to disable the counter by setting a ''disable'' bit in the CSR (bit 2) but writing to this bit seems to have no effect. The datasheet doesn't mention any other registers I should be accessing. Do I need to change anything else?

jatin · ‎2004-08-31

Posted on August 31, 2004 at 09:45

1. A write Access to counter low register CLR resets the counter value any time(timer enabled or disabled).

2. TIMD bit in CSR register is used to stop/disable the timer function. But you can still access the timer registers for example to reset the counter value, updating the timer prescaler etc. But counter will start as soon as you enable this bit.

pete3 · ‎2004-08-31

Posted on August 31, 2004 at 10:39

Jatin,

Thanks for your quick reply. Here is the code I am using to stop the timer (COSMIC 4k eval):

-----------------------------------

@interrupt void it_t16(){

Timeouts ++;

if (Timeouts == 1)

{

PDDR = 0;

}

else if (Timeouts == 2)

{

OutputAvailable = 1;

Timeouts = 0;

T16CSR = 0x04; /* Turns counter off */

}

-----------------------------------

vector.c:

void (* const _vectab[])() = {

it_dummy,

it_t16,

it_dummy,

it_canstatuschange,

it_canreceive,

it_dummy,

_stext, /* RESET */

};

-----------------------------------

As you can see this should disable the timer. The interrupt bits are being set for OCMP but as these interrupts are not enabled they should not be executed. I have also tried T16CSR |= 0x04 which does the same. it_dummy resets a number of unused interrupt bits and disables them in case this is required. I've not seen it executed yet (it also twiddles a pin).

sjo · ‎2004-08-31

Posted on August 31, 2004 at 12:05

I am guessing that you are using the timer in output compare mode.

When you receive an interrupt you will need to correctly clear the interrupt flag, otherwise the interrupt will be called forever.

OCF1 sequence - first read the SR register, then read or write the low byte of the OC1R (OC1LR) register.

Your sequence should be clear pending interrupt flag, then disable timer by clearing bit2 of the CSR register, eg. T16CSR &= ~(1<

Could you post your timer setup routine.

Regards

sjo

pete3 · ‎2004-08-31

Posted on August 31, 2004 at 12:53

Hi sjo,

I found that writing *any* value to any of the T16CR and CSR registers was causing the interrupt to fire, even 0x0 for the CRs and 0x04 for CSR. Writing to the CLR register starts the timer- so I wrote to this register and now the interrupts just don't stop :\ The default clock divisor of x4 is ok for me. Therefore I am doing nothing with these registers- no reads, no writes.

I've also C&P'd your line T16CSR &= ~(1<

T16CR1 &= 0;

T16CR2 &= 0;

to the ISR which has made no difference.

Thanks for taking a look incidentally!

pete3 · ‎2004-08-31

Posted on August 31, 2004 at 13:11

Ok, ya got me, I am writing 0x20 to T16CR1 (this enables the overflow interrupt). Forgot to put that in previous post

pete3 · ‎2004-09-01

Posted on September 01, 2004 at 12:57

Ach. Turns out some legacy code was playing with the interrupt. Wrote it months ago and forgot about it. It was doing some playing with other registers and causing a similar output to what I was expecting from the timer interrupt- although screwy, which is why I thought the timer was all messed up.

Timer fine, legacy code altered, much embarassment all round.