SRAM not holding up

[s_abbot]

Posted on May 18, 2004 at 23:13

SRAM not holding up

[s_abbot]

Posted on May 17, 2011 at 12:00Hi I have a problem with a uPSD3234A, I have a backup super cap attached to PC2, and have enabled the backup function in the port definitions in PSDsoft. However if I write to the SRAM all is fine, can read it back while the power is up, however if I depower for more the 15secs then all I read back is rubbish. I have confirmed that the super cap is holding 4.2V for the entire time and that this does appear on PC2. Anythoughts, as non volitile ram is important to the project. Regards Stephen

[danielh1]

Posted on May 17, 2011 at 12:00

Have you defined the PC2 pin as ''VSTDBY'' in PsdSoft?

Daniel

[s_abbot]

Posted on May 17, 2011 at 12:00

Thanks for the interest Asterix, I have as you have said defined PC2, I have attached my .frm and .sum files so you can see if you can help any further. As you will see, I have simply defined the SRAM, rs0 into 0x0000 to 0x1FFF and the only prog memory is in fs0 0x0000 to 0x7FFF I just want to use the part as a basic 80c52 at this moment with the SRAM working hence a simple memory layout, 32k of prog is enough at this point. Everything seems fine, until I pull the power, the SRAM remains after a reset (but not power cycle).

Interestingly, I did define PC4 for pstby monitor, however if I monitor that pin, it remains at 0V at all times even when the supply is removed but the supper cap still in circuit. I take it all I have to do is define PC2 as you stated, I do not need to adjust any of the PortC registers in CSIOP, currently they are untouched just as the boot. look forward to your comments, and I will continue other options. Regards Stephen

[s_abbot]

Posted on May 17, 2011 at 12:00Don't worry, I have just qualified for the gumboot award, a small rewiring got the SuperCap to the real PortC2, and all is fine. Regards Stephen