STR730 CAN Clock

[philip1]

Posted on August 18, 2008 at 16:15

STR730 CAN Clock

[philip1]

Posted on June 28, 2006 at 07:28

Hi,

I am experimenting with the CAN interface on the STR730FZ2 processor and so far I have it transmitting a message in LoopBack mode. The only problem is, the bit-rate is completely wrong!! I chose CAN_BITRATE_250K but I can see on the oscilloscope that it is actually 1.13Mbits/sec!! This makes sense as my core clock is 36MHz and the C library talks about a CAN_CLK of 8MHz. My question is, what sets CAN_CLK and can I make adjustments with a prescaler or do I have to work out all the component timings to store in the BTR register? thanks for any help offered PhilipJ

[davidbellegarde9]

Posted on June 29, 2006 at 10:21

Hello,

If your Core CLK is 36 MHz and if you want a 250K bit rate for the CAN0. Please do the following after the initialization: CAN_EnterInitMode(CAN0, CAN_CR_CCE); CAN_SetTiming(CAN0, 11, 4, 4, 9); CAN_LeaveInitMode(CAN0); Regards, S

[mcu_guy]

Posted on August 18, 2008 at 16:15

Do these settings work? I am in a similar situation. I am working with a STR731FV2 with MCLK at 36MHz. I tried those settings and I am only seeing error frames on the CAN bus. Can someone show a break down of how those values were derived?

>>> If your Core CLK is 36 MHz and if you want a 250K bit rate for the CAN0. Please do the following after the initialization: CAN_EnterInitMode(CAN0, CAN_CR_CCE); CAN_SetTiming(CAN0, 11, 4, 4, 9); CAN_LeaveInitMode(CAN0); <<<