Posted on July 07, 2008 at 05:03 The attached STVD 4.0 project shows a bug of the ST7FOXA0 simulator.
According to the stimuli file ''Bug.in'', after 64000 clock cycles there are an input capture and a timebase event.
The corresponding interrupt handlers are correctly prioritized as reported in the datasheet: first the input capture one, then the timebase one.
The simulator bug deals with the missing LTCSR_TBF clearing that the hardware does after a read to LTCSR, which is exactly the intended side effect of the instruction:
BTJF LTCSR,#LTCSR_TBF,IC_End
Since IC_ISR clears LTCSR_TBF LTCSR_TBF while the timebase interrupt request is waiting to be serviced, TB_ISR should not be executed but this does not happen.
Regards
EtaPhi
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Attachments : TbIcBug.zip :
https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006I08H&d=%2Fa%2F0X0000000bU4%2F_KRoRxI1A1mfnHAJcRUmOZKpZ9vsvkzg4bUa0ugZekc&asPdf=false
