72Lite25/29 High Idd problem

[drubinst]

Posted on December 23, 2004 at 08:00

72Lite25/29 High Idd problem

[drubinst]

Posted on December 20, 2004 at 22:02

I would appreciate any help with the following problem on the 72Lite25 and 29.

Randomly during turn on the device seems to latch in a high Idd consumption ( above 200ma as opposed to below 10ma normally ) once in this mode the device tends to remain in it even after resets or power recycle. The device is still fully functional ( pwm, a/d, I/O and code OK ) but obviously will overheat. All used I/O are clamped to Vdd ( close 7805 with 22u and 01u), unused I/O programmed as push pull outputs, reset and ICCCLK pulled up with 4K7. Please help asap before I am forced to give up on ST for this mid volume project. Thanks Darub

[wolfgang2399]

Posted on December 21, 2004 at 06:05

Just an idea:

Known in CMOS devices there is a problem with floating inputs. If the input comes to an state, where neither the upper nor the lower internal MOSFET is really off you can get a high internal current from Vdd to Vss. So make sure, that all digital input ports - especially the unused - have defined high ore low values at any time. I have no idea what happens with the analogue inputs if you don't use them and switch them to digital floating mode. Hope it helps WoRo

[jatin]

Posted on December 22, 2004 at 02:53

1. ''All used I/O are clamped to Vdd ''

Can you pls explain this ? What do you mean by clamped ? Is it pull-up ? if yes, what is the need ? 2. For Un-Used IOs, can you pls try to force them to floating input ( reset state) and put an external pull-up ? 3. Can you pls try to isolate a problem with the part of code causing a problem ? selective execution of firmware .. 4. Make sure that there is no very low value resistane which is loading the IOs. 5. Can you pls provide the schematic ? Did you check if 5V supply is stable and not oscillating to 6V etc ? Can you try with a different supply ?

[drubinst]

Posted on December 22, 2004 at 02:58

Thanks for your feedback Woro.

The unused I/O are all defined as outputs and left unconnected. The micro get into this mode during a significant di/dt transient in its vecinities and once in high Idd it remains there even after a reset - permanently. I start having the impression it may be an emc issue since it was not happening on the breadboard but it it occuring quite consistently on the first pcb layout with presumably much better ground planes.

[drubinst]

Posted on December 22, 2004 at 03:16

Thanks for your feedback Jatin.

Please see below: 1. I clamped the used I/O with a diode to Vdd. 2. I will try with a pull up, but is it a problem setting the unused I/O to outputs? 3.I am using Realizer - any suggestions on how to do it in that environment? 4.The power supply is perfectly stable and no overshoots are present. In fact besides the normal LVD resets there are others corresponding to the, I presume , watchdog which start occuring just before the failure.

[wolfgang2399]

Posted on December 22, 2004 at 09:39

No further idea - but:

As you describe your problem it seems to be a typical latchup effect. - Latchup appears if the input/output of a CMOS-device gets over-or undervoltage. Normaly the internal clamp-diodes will prevent from this. If you force a under-/overvoltage to the port with a powerfull driver or so, you can break the internal clamp-diode - in your case especiallly for V_in- Latchup might appear if an externally given voltage at input/output has a very short rise time. But that is no more known as a problem because of good ESD-protection in modern devices. - At least you can get a latchup if you have a very short rise time on your supply voltage of the controller. Latchup usually should not be any problem in modern CMOS devices. Thus the upper points are given although I don't see the reason for the latchup with all I know about your application. But still I'm shure - it's a latchup. Anyhow I hope it helps WoRo

[drubinst]

Posted on December 22, 2004 at 22:19

Thanks for your reply WoRo.

I think the micro is being affected by strong current pulses in its vecinities. Measuring with a small loop ( 10mm diameter ) under the micro I can pickup, just before the fault occurs, induced current pulses in the order of 60ma and up to 250mv for 10us, would that be enough to ''fry'' the micro?

[wolfgang2399]

Posted on December 23, 2004 at 08:00

Hi Darub,

measured ''60mA with a small loop'' is an EM pulse that can result latchup in the µC via injection into any line. Because I neither know your application nor the interior of the µC I will only ask you to study some notes about EMC conform PCB design. Combining low signal and power signal on one PCB you have to follow strict rules to meet the EMC requirements. In any case you should avoid - high current or voltage pulses or slopes close to your µC - big loops And prior to all take care for a proper GND-design e.g. strictly seperate µC-GND area (Vdd) from other GND areas. We are using ST7 µCs on our applications, driving with power semiconductors loads up to 1kW and have got best results - especially with the ST7 µCs. I only found one technical note that can give you some information under

http://www.st.com/stonline/books/pdf/docs/10692.pdf

And pls have a look at chapter 13.7 of the ST7LITE2 datasheet. I hope the information is not too poor for your problem but I think you'll find some more rules for EMC conform PCB design inside the internet - or read a good book. 😉 Best Regards WoRo