Posted on July 19, 2005 at 05:42I have found some inconsistences between the datasheet and the 71x_lib to do with the APB regisiters.
In version 6 of the STR71x data sheet(p338) it clearly states
''Bit 0 controls the peripheral in position 1 (I2C0 for APB1 or XTI for APB2) and so on''.
However if you look at the #define in APB.h these are wrong and start at bit 1
from apb.h v3.0 (latest version on st web site)
/* APB1 Peripherals */
#define I2C0_Periph 0x0002
#define I2C1_Periph 0x0004
#define UART0_Periph 0x0010
#define UART1_Periph 0x0020
#define UART2_Periph 0x0040
#define UART3_Periph 0x0080
#define USB_Periph 0x0100
#define CAN_Periph 0x0200
#define BSPI0_Periph 0x0400
#define BSPI1_Periph 0x0800
#define HDLC_Periph 0x2000
/* APB2 Peripherals */
#define XTI_Periph 0x0002
#define GPIO0_Periph 0x0004
#define GPIO1_Periph 0x0008
#define GPIO2_Periph 0x0010
#define ADC12_Periph 0x0080
#define TIM0_Periph 0x0200
#define TIM1_Periph 0x0400
#define TIM2_Periph 0x0800
#define TIM3_Periph 0x1000
#define RTC_Periph 0x2000
#define WDG_Periph 0x4000
#define EIC_Periph 0x8000
Also the EIC_Periph is placed at bit 15 even though the datasheet would appear to have bit 15 as a reserved bit. Although the discription is not clear as the text doesnt mention bit 15.
from datasheet -
Bit 31:16 = Reserved, must be kept at reset value (0).
Bit 14:0 = Peripheral Clock Disable (14:0)
What happend to bit 15 ?
Perhaps on the next release of the 71x library/datahseet you could correct whichever is wrong.
Ben
