wrong read RCCU registers values

[yves2]

Posted on January 22, 2007 at 06:36

wrong read RCCU registers values

[yves2]

Posted on January 19, 2007 at 10:38

Hello,

I'm trying to read a RCCU register (CFR). I so have to put the Core clock divisor to value 1. But if I read CFR register right after putting MDIVR to 0 (ie MCLK divisor to 1), I sometimes read wrong values. On the other hand, if I insert a NOP instruction before reading CFR, the read value is always correct. Here after is my source code. What is sometimes wrong... PCU->MDIVR = 0x0000 ; // Set Main clock divisor to 1 RCCU_CFR = RCCU->CFR ; // Sometimes, read value is wrong :-? what is always right.... PCU->MDIVR = 0x0000 ; // Set Main clock divisor to 1 __asm { NOP } RCCU_CFR = RCCU->CFR; // Read value is always correct :p Is any stabilization/synchronisation necessary after modifying the MainClock divisor ? Thanks for your help !

[mohamed23]

Posted on January 19, 2007 at 20:29

Dear DEVOS,

Before setting ''PCU->MDIVR = 0x0000 ; // Set Main clock divisor to 1'' what is your old PCU-MDIV value ? I think that by default ( Reset Value) of this register is equal to 0, so the MDIV facter is already set to One. There is a note in the STR71x Reference Manual ( PRCCU part ) saying that if this facter is diffrent from 0 , the PRCCU register mainly the CFR is not accessible anymore. This is due to the fact that the PRCCU block is always clocked by the RCLK clock which is at this case a multiple of the MCLK ( Core & memory) Clock. Assuming for example : MDIVR = 0x0001 , and RCLK = 32MHz at this case MCLK = 16MHz ( which is the the Frequency of the CPU & memory) Excuting your code will probably give you in assembler ( with high speed optimisation) R0 : Register containing you variable RCCU_CFR R1 : Register containing the address of PCU->MDIVR R2 : Register containing the address of RCCU->CFR Instruction 1 : MOV R0, #0 : One Cycle of CPU = 16MHz Instruction 2 : STR R0 , [R1] : 2 Cycles of CPU = 16MHz Instruction 3 : LDR R0,[R2] : 3 Cycles of CPU = 32MHz or 16MHz ??? The problem may be explained in the transition after the executing of instruction 2 And the effective switching of the MCLK Frequency from 16 to 32MHz just before Executing instruction 3: if the MCLK is still at 16MHz you will get wrong data as Explained in ST RM document, however if the MCLK is already switched to 32MHz You will get the right data. However, In my analysis I forget the 3 stage Pipeline effect ( Fetch , Decode and Excecute ) which may complicate the task here since while in execute stage Of inst2 , the CPU has already fetched and decoded instruction 3 at a Frequency of 16MHz..... !!! So now, to execute your code safely you have just to a add extra instructions Like NOP or ''MOV R0, RO'' to avoid this spirious situation ! I hope that this may help you 🙂 Rave

[yves2]

Posted on January 22, 2007 at 06:36

Quote:

There is a note in the STR71x Reference Manual ( PRCCU part ) saying that

if this facter is diffrent from 0 , the PRCCU register mainly the CFR is not accessible anymore. This is due to the fact that the PRCCU block is always clocked by the RCLK clock which is at this case a multiple of the MCLK ( Core & memory) ClockThat's why I set MDIVR to 0. Indeed, depending on the application, I don't know what's the previous value of this register. What is very confusing is that it is a random problem : sometimes value is right, sometimes it's wrong ! :o Nevermind, adding a NOP instruction seems to correct this problem, so... Thank's Rave.