GPIO performance

[sebestajan]

Posted on January 24, 2007 at 16:46

GPIO performance

[roger_lynx]

Posted on May 17, 2011 at 09:32

So, in 96 MHz CPU we can get maximum frequency 96/6=16MHz.

Is anyone in doubt with my expectation? Please help me to find hidden problems... I am ''in doubt with your expectations''. 🙂 the key is point 3): jump to point 1) The same type of discussion was going on with LPC2k in yahoo group for many weeks, see what you can read there to educate yourself: http://tech.groups.yahoo.com/group/lpc2000/message/16114 The problem is not hidden, though. The solution is, at this time.

[mark9]

Posted on May 17, 2011 at 09:32

The GPIO switching rate depends on a lot of things. My theory (which I will gladly have debunked) is that 6 PCLK clock cycles are needed for every GPIO pin change. A full cycle is then 12 PCLK cycles. If you are running PCLK=RCLK=MCLK=PLL = 96MHz, then the fastest square wave you could get out using bit-banged GPIO is 8 MHz.

Note, this has nothing to do with instruction cycles, although if you don't use the PFQBC on, AHB buffer on (CP15 configuration), write to buffered APB ports (0x40000000), then you won't get 8 MHz. I was able to get 4MHz at 48MHz PLL, but I haven't figured out how to get 96MHz working... I think this is unrelated.

[sebestajan]

Posted on May 17, 2011 at 09:32

How many CPU cycles needed to toggle GPIO pin in a loop? I think only three instructions are needed, count with me:

1) toggle register XX 2) write register XX to I/O port YY 3) jump to point 1 So we need 6 instructions for one period of square signal produced at the output on GPIO pin. So, in 96 MHz CPU we can get maximum frequency 96/6=16MHz. Is anyone in doubt with my expectation? Please help me to find hidden problems... ---------------- Another problem is how many instructions it can take reading data from a piece of on-chip memory (64k 32-bit wide on-chip RAM) and write the data to 8-bit wide GPIO, did anyone tested this sample application? --------------- Last problem of GPIO, is the reception. Imagine data bytes has to be received in the speed of about 5 MBytes/s, is there DMA channel which can be activated on the rising (or falling) edge of external signal? [ This message was edited by: janse on 02-10-2006 16:14 ]