Remapping bank 1 using keil

[craig239955_st]

Posted on February 23, 2007 at 11:52

Remapping bank 1 using keil

[craig239955_st]

Posted on May 17, 2011 at 09:35

Hi,

I want to build the RS232 bootloader. Is it possible to remap bank 1 at 0x00 using keil compiler (µVision 3.50) and ulink. There is a checkbox ''startup'' in the settings of ROM areas to tell the compiler where to place the startupcode. However, I do'nt think this will remap bank 1. Some time ago I had do replace a STR912 device after experiments with remapping, because I was unable to erase or program the flash... So I have to be sure ! Thanks Luc

[jas]

Posted on May 17, 2011 at 09:35

Hi,

It is my understanding that the special remapping bits can only be programmed using ST CAPS utility and ST FLASHlink cable (PC parallel port based). WHEN OH WHEN will we be able to use our J-Link, U-Link (etc) JTAG devices with CAPS ? I hope ST are talking to vendors like Keil, IAR......... Maybe the Moderators can find out please.

[mehdi239955]

Posted on May 17, 2011 at 09:35

Hi Arm-Wrestler,

Quote:

It is my understanding that the special remapping bits can only be programmed using ST CAPS utility and ST FLASHlink cable (PC parallel port based).

The R-link (USB device) from Raisonance is fully supported by ST CAPS, be sure that other JTAG tools are planned to be supported by CAPS 8-) . Moreover, i want to let you know that RIDE (version 746 P1 P2) from Raisonance supports the bank remapping and it could be a good alternative to CAPS. IAR will ,in near future, support the bank remapping... (Next version) :p Best regards MBS [ This message was edited by: MBS on 21-02-2007 14:23 ]

[craig239955_st]

Posted on May 17, 2011 at 09:35

Thank you for fast response !

I asked the same question in the Keil forum. No answer so far... I am about to buy the keil compiler (over 3000€!). May be I have to look for another vendor, I think there is very little support from Keil.. Luc

[jgoril]

Posted on May 17, 2011 at 09:35

Quote:

On 21-02-2007 at 14:32, Anonymous wrote: ... Note: The JTAG clock for CPU programming must be at least 8 times slower than the CPU clock (which is typically 25MHz XTAL). This means that you can typically select up to 2MHz JTAG clock). ICP algorithms in Turbo Mode do not have that constraint but the Turbo Mode is not working completely due to a chip problem. ... Hello. I'm interested in to know more about turbo mode and chip problem. Please, can you write more? Thank a lot... Jozef