Interrupt priorities

sjackson · ‎2007-11-20

Posted on November 20, 2007 at 18:59

joseph239955 · ‎2011-05-17

Posted on May 17, 2011 at 12:18

It is in section 5.3.2 of the Cortex-M3 Technical Reference Manual.

The actual priority group control register is part of the Application Interrupt and Reset Control Register (table 8.16).

sjackson · ‎2011-05-17

Posted on May 17, 2011 at 12:18

I'm trying to configure the STM32's NVIC to enable various interrupts. The firmware library reference manual mentions priority groups, preemption priorities, and sub-priorities. However, there is no mention of any of these in the reference manual.

Could someone please give me a rundown on what these options do and/or point me to the appropriate documentation?

Thanks!