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vector.s for Anglia IDEaliST

gflasza
Associate II
Posted on November 21, 2007 at 13:57

vector.s for Anglia IDEaliST

14 REPLIES 14
mehdi239955
Associate II
Posted on May 17, 2011 at 09:41

Hi

Can you provide me with more details.

Did vectors.s works with only one interrupt?

regards

MBS,

[ This message was edited by: MBS on 10-04-2007 11:26 ]

gflasza
Associate II
Posted on May 17, 2011 at 09:41

Hi

I looking for working vector.s file for Anglia Compiler

I've got the standard vectors.s, but it doesn't work with two interrupts (from VIC0 and VIC1)

[ This message was edited by: GrzesiekFl on 10-04-2007 10:33 ]

gflasza
Associate II
Posted on May 17, 2011 at 09:41

I have two interrupts : one from TIM0 and one from UART0. When I use two interrupts I lose chars from UART0, but when I use ONLY TIM0 interrupts it works correctly

mehdi239955
Associate II
Posted on May 17, 2011 at 09:41

Hi ,

Please find attached a project (RIDE/IAR/RVDK) with two interrupts and note that RIDE is using GNU compiler (GCC-ARM) so, you'll find the necessary modification needed to vector.s in 91x_init.s .

Regards,

MBS

[ This message was edited by: MBS on 13-04-2007 15:51 ]

kmshim
Associate II
Posted on May 17, 2011 at 09:41

Hi,

Maybe your problem will be the cause of nested interrupt.

also, I had same problem. would you modify the IRQ handler as following in the vect.s

IRQHandler

SUB lr,lr,#4 ;// Update the link register

SaveContext r0,r12 ;// Save the workspace plus the current

;// return address lr_irq and spsr_irq

LDR r0, = VectorAddress

LDR r0, [r0] ;// Read the routine address

;//LDR r1, = VectorAddressDaisy

;//LDR r1, [r1]

;// Padding between the acknowledge and re-enable of interrupts

;// For more details, please refer to the following URL

;//

http://www.arm.com/support/faqip/3682.html

;//NOP

;//NOP

;//MSR cpsr_c,#0x1F | I_Bit ;// Switch to SYS mode and disable IRQ modified by KMSHIM, 2007/03/15

;//MSR cpsr_c,#0x1F ;// Switch to SYS mode and enable IRQ

STMFD sp!,{lr} ;// Save the link register.

LDR lr, = IRQ_ReturnAddress ;// Read the return address.

BX r0 ;// Branch to the IRQ handler.

IRQ_ReturnAddress

LDMFD sp!,{lr} ;// Restore the link register.

;//MSR cpsr_c,#0xD2 | I_Bit ;// Switch to IRQ mode and disable IRQ

LDR r0, = VectorAddress ;// Write to the VectorAddress to clear the

STR r0,[r0] ;// respective interrupt in the internal interrupt

LDR r1, = VectorAddressDaisy ;// Write to the VectorAddressDaisy to clear the

STR r1,[r1] ;// respective interrupt in the internal interrupt

RestoreContext r0,r12 ;// Restore the context and return to the...

;// ...program execution.

good luck!!

best regards,

KMSHIM

mehdi239955
Associate II
Posted on May 17, 2011 at 09:41

Hi KM SHIM,

i think the problem of spurious interrupt are now solved with the different modifications that we have done on Vector.s and it.c .

have a look to IRQ project which i send previously.(waiting for your feedback 8-) )

Regards,

MBS

:-]

[ This message was edited by: MBS on 12-04-2007 11:52 ]

kmshim
Associate II
Posted on May 17, 2011 at 09:41

Hi, MBS

Mode switch that you have done have been implemented in the IRQ handler.

I think that there are jsut differences as like nested interrut and writing to VICx->VAR.

Are there any difference in the your code?

best regards,

KM SHIM

mehdi239955
Associate II
Posted on May 17, 2011 at 09:41

hi,

I didn't understand your question :( .

The example which i sent,is a solution to generate correct nested interrupt with VIC0 and VIC1 without any conflict .

did you try it?

Regards,

MBS

[ This message was edited by: MBS on 12-04-2007 16:24 ]

mehdi239955
Associate II
Posted on May 17, 2011 at 09:41

hi all,

i've done the portage of IRQ project to anglia IDE. :-]

keep me informed about any issue.

regards.

MBS 8-)

[ This message was edited by: MBS on 13-04-2007 17:38 ]