str 911fm44 first steps

[mariusz2]

Posted on April 06, 2007 at 12:00

str 911fm44 first steps

[mariusz2]

Posted on May 17, 2011 at 09:40

Hi all.this is my first steps to programing in ARM. I began programming software in str911fm44. I use STX-link and raisonanse development tools. I have several problems:

1) How connect j-tag 20 pins to str911fm44 ? I d'not find to ST sites example 2) I connect j-tag connetor via example F-link (st www sites) 14 pin connector. At present time, I can olny programing flasch memory, and run program it is OK, in debug mode I Have message ''unable yo communicate witch target CPU''. How run i debug mode (may by jtag conetetcor is connected improper (badly)? 3) I have a problem witch initialize PPL clock mode all function returns error: (SCU_PLLCmd(DISABLE)-ERROR,SCU_PLLFactorsConfig(_PLL_N, _PLL_M, _PLL_P)-ERROR,SCU_MCLKSourceConfig(SCU_MCLK_OSC)-ERROR, without one ( SCU_PLLCmd(ENABLE)) I use library stdlib from St site If possible plesase send me example with initialise PLL clock (I Use crystal 11,0592 Mhz)value PLL_M, PLL_P PLL_N generate caps software. All examples from st site not run. only function printf is ok. while(1) { printf(''U''); } I obsere wavwform to scope uart0, node TX0, spped is not compatybile with standards uart speed, one frame about 2 ms please help me. best regards Mariusz

[mtraman]

Posted on May 17, 2011 at 09:40

HI

hav u used any board chip definitions .bcd or some config file that contains the microcontroller specific register addresses etc. For the jtag programmer to program the uc correctly it has to know the length of the different parts in the scan chain. Once u do this the jtag hardware can communicate with the uc.

[mehdi239955]

Posted on May 17, 2011 at 09:40

Hi all,

Quote:

How connect j-tag 20 pins to str911fm44 ?

Concerning, the JTAG connection I think this attached file will solve your problem. :-]

Quote:

in debug mode I Have message ''unable yo communicate witch target CPU''. How run i debug mode (may by jtag conetetcor is connected improper (badly)?

I think the oscillator you're using has a responsibility in that. Therefore, in order to have a normal JTAG connection, the JTAG speed should be at least 10 times slower than the MCU's freq so i propose 1000Khz as JTAG speed. I understood that you’re using RIDE debugger, can you precise which version (Build Number )

Quote:

If possible plesase send me example with initialise PLL clock (I Use crystal 11,0592 Mhz)value PLL_M, PLL_P PLL_N generate caps software.

Find attached a header file containing the PLL configuration. Best regards, MBS [ This message was edited by: MBS on 05-04-2007 12:10 ]

[mariusz2]

Posted on May 17, 2011 at 09:40

Thank you for help, where connect net DBGRQS to node STR 911fm44

all sigal J-tag i connect OK, without DBGRQS I d'not know where this connect. My program is run Ok when, I diretly set register, for exampe SCU->GPIO4...... or directly adress set port #define PORT4 GPIO4->DR[0x3FC] while(1) { PORT4=0xff; PORT4=0; } this is OK if I use Library STDLIb from ST, end compiled Raisonace tools, I have problems with UART I d'ont send char from serial port my configuration: UART_Cmd(UART0, ENABLE); UART_Cmd(UART1, ENABLE); UART_DeInit(UART0); UART_DeInit(UART1); UART_InitStructure.UART_WordLength = UART_WordLength_8D; UART_InitStructure.UART_StopBits = UART_StopBits_1; UART_InitStructure.UART_Parity = UART_Parity_No; UART_InitStructure.UART_BaudRate = 9600; UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_None; UART_InitStructure.UART_Mode = UART_Mode_Tx_Rx; UART_InitStructure.UART_FIFO = UART_FIFO_Enable; UART_InitStructure.UART_TxFIFOLevel = UART_FIFOLevel_1_2; UART_InitStructure.UART_RxFIFOLevel = UART_FIFOLevel_1_2; UART_Init(UART0, &UART_InitStructure); UART_Init(UART1, &UART_InitStructure); while(1) { UART_SendData(UART0,'U'); } May by is nessery aditional config GPIO3 (node uart0)? I will use library ST to programing software, because I d'not time learn peripherial CPU One hardware problem: I use crystal 11,0592 MHz I will multipled *8 I use walue from cap software #define _PLL_M 6 // M (1 <= M <= 255) value for phase lock loop #define _PLL_N 96 // N (1 <= N <= 255) value for phase lock loop #define _PLL_P 2 if I use this CPU not work I must use modified value _PLL_P 3 this setep give me ony phase loop *4 if i use M-144, P-4 M-3 I have PLL*6 This is maximum, where is bug?