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RTC Count and Standby mode

ngaylard
Associate II
Posted on September 01, 2009 at 14:05

RTC Count and Standby mode

4 REPLIES 4
ngaylard
Associate II
Posted on May 17, 2011 at 13:22

Hello,

I am developing a system where we use standby mode extensively and use the RTC to wake the unit. All this works without any problems but it appears that on waking the RTC counter value is reset to 0, ideally we want to retain the value as it relates to time of day on the system. Any help would be appreciated.

-- As a side note the wake up pin is forced into input pulldown mode, when enabled meaning that you can't achieve low power with an open drain device connected to wake, this is not a problem when you plan for it :-?

16-32micros
Associate III
Posted on May 17, 2011 at 13:22

Dear ArmNewbie,

The RTC core and clock configuration (RCC_BDCR register) are in the Backup domain, which means that RTC setting and time are kept after reset or wakeup from Standby mode.

After a power reset has occurred or The MCU has just woken up from Standby mode or Stop mode, access to the Backup registers and RTC is disabled and the Backup domain(BKP) is protected against possible parasitic write access

To enable access to the Backup registers and the RTC, proceed as follows:

1) Enable the power and backup interface clocks by setting the PWREN and BKPEN bits in the RCC_APB1ENR register

2) Set the DBP bit the Power Control Register (PWR_CR) to enable access to the Backup registers and RTC.

For more details refer to RM0008 , Sub-section ''Reading RTC registers''

Hope this helps you.

Cheers,

STOne-32.

ngaylard
Associate II
Posted on May 17, 2011 at 13:22

thanks for the reply. I had not re-enabled access to the backup domain and it now appears to be working.

ngaylard
Associate II
Posted on May 17, 2011 at 13:22

Quote:

On 29-08-2009 at 22:10, Anonymous wrote:

Dear ArmNewbie,

The RTC core and clock configuration (RCC_BDCR register) are in the Backup domain, which means that RTC setting and time are kept after reset or wakeup from Standby mode.

After a power reset has occurred or The MCU has just woken up from Standby mode or Stop mode, access to the Backup registers and RTC is disabled and the Backup domain(BKP) is protected against possible parasitic write access

To enable access to the Backup registers and the RTC, proceed as follows:

1) Enable the power and backup interface clocks by setting the PWREN and BKPEN bits in the RCC_APB1ENR register

2) Set the DBP bit the Power Control Register (PWR_CR) to enable access to the Backup registers and RTC.

For more details refer to RM0008 , Sub-section ''Reading RTC registers''

Hope this helps you.

Cheers,

STOne-32.

I have done some further investigation and I am confused/puzzled as it appears that I am doing exactly what ST's examples do.

I have a function to configure the RTC

void RTCConfiguration(void)

{

PWR_BackupAccessCmd(ENABLE);

if(PWR_GetFlagStatus(PWR_FLAG_SB) != RESET)

{

PWR_ClearFlag(PWR_FLAG_SB);

RTC_WaitForSynchro();

}

else

{

RCC_RTCCLKConfig(RCC_RTCCLKSource_LSI);

RCC_RTCCLKCmd(ENABLE);

RTC_WaitForSynchro();

RTC_WaitForLastTask();

RTC_SetCounter(1250954471);

RTC_WaitForLastTask();

RTC_ITConfig(RTC_IT_ALR, ENABLE);

RTC_WaitForLastTask();

RTC_ITConfig(RTC_IT_SEC, ENABLE);

RTC_WaitForLastTask();

RTC_SetPrescaler(40000);

RTC_WaitForLastTask();

}

}

From the ST user manual on the registers synchronised flag

''Bit 3 RSF: Registers Synchronized Flag

This bit is set by hardware at each time the RTC_CNT and RTC_DIV registers are updated

and cleared by software. Before any read operation after an APB1 reset or an APB1 clock

stop, this bit must be cleared by software, and the user application must wait until it is set to

be sure that the RTC_CNT, RTC_ALR or RTC_PRL registers are synchronized.

0: Registers not yet synchronized.

1: Registers synchronized''

My code hangs waiting for the RSF flag to go to '1', however if I understand the paragraph above I need to interact with either the DIV or count registers in order for it to be set by hardware. If this is the case what ''safe'' method can I ensure synchronisation without corrupting the count value?