STR752FR2 got stuck during FLASH erase

romano · ‎2008-02-05

Posted on February 05, 2008 at 13:41

romano · ‎2008-01-29

Posted on January 29, 2008 at 20:41

Hello,

I have a severe problem with STR752FR2, during FLASH erase.

In my application, first I download a bootloader program, with a J-Link (IAR ARM compiler V5.11). All bootloader downloads go ok (50 out of 50 PCB). Then the bootloader loads the real firmware by CAN bus, first ERASING then WRITING.. 13 CPUs out of 50 got stuck during the ERASE procedure.

The ERASE procedure, taken by ST library with some simplification, is very simple. If I step through with J-Link, the ERASE procedure works. If I run the device (no step, but RUN), the ERASE will not work on these PCB (but the same program works perfectly on the others PCB). Same behaviour if the CPU is running without the debugger at all.

Prior to erasing, there is a procedure to unprotect all sectors.

When I stop the debugger after a lock, I can see that the LOCK bit in CR0 is 0 (so I can read the other FLASH registers), but the BSY0 is still 1, and the WMS bit is still 1 (of course SER bit is at 1), and I cannot do anything to unlock the system apart from reset.

Of course the instructions that checks for these bits are located in RAM.

Info on HW:

- 8MHz crystal, DIV by 2 is enabled, all clocks (CPU, buses and peripherals) are 32MHz

- I tried with both FLASH BURST mode enabled and disabled, but no difference

- there is an improvement if I don't init the CAN interface before erasing, but this seems nonsense

- all stacks are huge

- no interrupts are enabled nor served

- the program is written for the 128k FR1, and ignores the extra FLASH in the FR2.

- the ERASE procedure is for all BANK0 sectors, except Sectors 0 and 1 (8+8k) where the bootloader is located.

I have only one hypothesis still to be checked:

the FLASH erase/write controller doesn't work well @32MHz...

Please consider (if you can) this matter really urgent, thank you.

[ This message was edited by: rberna on 30-01-2008 12:19 ]

romano · ‎2008-01-29

Posted on January 30, 2008 at 06:35

I attached the C code for better diagnosis.

******************************************************

void main(void)

...

FLASH_disable_write_protection();

FLASH_erase_sectors(MAINPROGRAM_SECTORS_BANK0);

FLASH_disable_write_protection();

FLASH_erase_sectors(MAINPROGRAM_SECTORS_BANK1);

....

------------

void FLASH_disable_write_protection(void)

{

FLASH_CR0 = FLASH_SPR_MASK; // CMD = SET PROTECTION

FLASH_AR = FLASH_NVWPAR_ADDRESS;

FLASH_DR0 = 0xffffffff; // Temporarily Enable Writing

FLASH_exec_and_wait();

}

-----------

void FLASH_erase_sectors(u32 FLASH_Sectors)

{

FLASH_CR0 = FLASH_SER_MASK; // CMD = Sector Erase

FLASH_CR1 = FLASH_Sectors;

FLASH_exec_and_wait();

}

---------------

__ramfunc void FLASH_exec_and_wait(void)

{

FLASH_CR0 |= FLASH_WMS_MASK; // WMS = 1 to start operation

__no_operation();

while(FLASH_CR0 & 0x00000010); // wait for LOCK to be reset

__no_operation();

while(FLASH_CR0 & 0x00000006); // wait for BSYAx to be reset

}

--------

[ This message was edited by: rberna on 30-01-2008 11:05 ]

[ This message was edited by: rberna on 30-01-2008 12:21 ]

romano · ‎2008-01-31

Posted on January 31, 2008 at 19:07

Hello, I solved the problem, simply by lowering the clock to 2MHz (switching from PLL 64MHz/2=32MHz to OSC4M 4MHz/2=2MHz), before calling erase functions, then raising again after. All of the CPUs that got stuck during erase, now erase perfectly.

SO IN MY OPINION THERE IS SOMETHING ''MISSING'' IN ST DOCUMENTATION AND/OR SOME PROBLEMS WITH MY CHIPS.

COULD I KINDLY HAVE AN ANSWER FROM AN ST GUY?

Thank you.

jpeacock2 · ‎2008-02-04

Posted on February 04, 2008 at 20:15

I seem to be having a similar problem on an STR750FV2T6, when I try to unprotect flash bank 1 from RAM. The flash error register shows 0x0001, only the ERR bit set after attempting an unprotect write. If I step through it on the debugger it works, but not when running from RAM. CKSYS clock speed is 60Mhz (PLL x 15, 8Mhz xtal and XTDIV2).

I am not clear on the description of reducing clock speed. Which clock did you slow down, CYSYS? And how did you get to 2Mhz if you have an 8Mhz external xtal (I do the same), since the /2 should yield 4Mhz, not 2Mhz?

jpeacock2 · ‎2008-02-04

Posted on February 04, 2008 at 21:42

Posted too soon...It turns out I can program flash bank 1 from flash bank 0 at the 60Mhz CKSYS rate on an STR750FV2, as long as the first flash operation (i.e. the bank unprotect) runs from RAM, a requirement documented in the ST flash programming guide.

romano · ‎2008-02-05

Posted on February 05, 2008 at 11:32

I used 8MHz crystal, but XTDIV2 is on, so I get 4MHz (same as having a 4MHz crystak with XTDIV2 not enabled), after this the PLL multiplies by 16 to get 64MHz, then I divide CLKSYS by 2 (my setting, for me 32MHz are more than enough). So HCLK = PCLK = 32MHz. If I switch off the PLL, the main clock is 4MHz (8MHz divided by two by XTDIV2), that finally is divided by 2 (my setting) giving 2MHz.

Regarding your solution, please note that the very first erase is **indeed** done while executing in RAM:

-

vvvvvvvv code is in RAM

__ramfunc void FLASH_exec_and_wait(void)

{

FLASH_CR0 |= FLASH_WMS_MASK; // WMS = 1 to start operation

...

-

So I still cannot explain why, any other idea?

Thank you

[ This message was edited by: rberna on 05-02-2008 16:03 ]

jpeacock2 · ‎2008-02-05

Posted on February 05, 2008 at 13:41

The one major difference I can see between your flash code and mine is that you test LOCK and BSY separately. I test all three flags at once to wait for a flash operation to finish. I based it on the example in the FLASH_WaitLastOperation() library call from ST, but I hard code the bit test rather than call that routine.

Also, the only code I run from RAM is the bank unprotect, the very first operation to access flash programming, to get around the limitation of the flash unit. All other flash operations such as erase and write are run from flash bank 0, operating on sectors in flash bank 1.

I am running the flash routines with all interrupts disabled.