Posted on May 17, 2011 at 12:39Hi tibo,
When you say toggling a bit, I guess you mean that the software have no knowledge of previous state of the bit. In this case you need to read
the bit value first, and then write back. If the software already know what previous value is, then toggling the bit will only be one bit band write.
Assumed the toggle operation contains a bit band read and a bit band write, with only one (or a few) instruction between them. If this is a single processor system with no other bus master, you can use:
1) Set Fault mask,
2) Read bit,
3) Invert bit,
4) Write bit,
5) Clear fault mask
In this way, the only possible exception that can take place between the read and write would be NMI, which should be rare. This is NOT absolutely atomic, but should be sufficient for most of the applications.
However, since there is a DMA controller in STM32, and it is possible that the DMA controller changes the bit value between the read and write. Of course you can disable the DMA controller, or make sure that the DMA controller does not access to the same memory or peripheral (which would be a race condition anyway).
If you want to make sure there is no NMI between the read and write, you should use exclusive accesses. If any exception take place between the exclusive read and exclusive write, the exclusive write will return fail status and the actual write will not be carried out.
To use exclusive access, you need to code it in assembler (as far as I know C compiler does not generate exclusive access instruction). For example,
LDR r0,=DeviceRegisterAddr ; Note: not bit band alias address
LDR r3,=BitToInvert ; E.g. 0x1 for bit 0, 0x2 for bit 1, etc
loop
LDREX r1,[r0] ; Read the register
EORS r1, r3 ; invert the bit
STREX r2, r1,[r0] ; Write to register.
; r2 is returned exclusive status
CBZ r2, WriteDone ; if r2 is 0, STREX was succeed
B loop ; otherwise retry
WriteDone
Using exclusive accesses can detect if any exception had taken place between the read and the write. Exclusive access mechanism can also support multiple bus masters, but I don't know if STM32 has exclusive access monitor on its memory bus. If it does, it could detect if DMA has accessed to the same peripheral and cause the LDREX to be executed again.
Even if it doesn't, just make sure the DMA controller won't access to same location and it should be okay.
