Five volt tolerant I/O's implementation.

hans5 · ‎2007-11-23

Posted on November 23, 2007 at 14:29

hans5 · ‎2011-05-17

Posted on May 17, 2011 at 12:18

Hello,

How is the protection of 5V tolerant I/O pins implemented?

According to the datasheet, a FT pin accept voltages up to 5.5V

However, the datasheet also indicates (in de description of the I2C interface characteristics) the presence of a protection diode between an I/O and Vdd.

The reference manual also shows this protection diode to Vdd in Figure 9, Basic structure of an I/O port pin.

- How can a pin be protected by a diode to Vdd while accepting 5.5V levels?

- Do I need external circuit (like on the STM3210B-EVAL board) to interface the I2C pins to a 5V I2C device?

Thanks in advance for your answer!

Hans Rosenbrand

16-32micros · ‎2011-05-17

Posted on May 17, 2011 at 12:18

Dear hans1,

All STM32 FT Pins are 5 Volts tolerants (Either input or output),In fact

there is no protection Diode to VDD but to VDD_FT Rail different from VDD is able to go to 5.5 without any interference with VDD.

For more details on the Implementation Please refer to the new Version of the STM32 Reference Manual

http://www.st.com/stonline/products/literature/rm/13902.pdf

: Section 5 ( Figure 10).

You don't need an external Circuit to interface 5Volts I2C pins. The STM3210B-EVAL board was designed with some early engineering prototypes and the schematics should be updated as well.

I hope this helps you 😉

Regards, STOne-32

[ This message was edited by: STOne-32 on 23-11-2007 18:59 ]