Posted on May 17, 2011 at 12:48slawcus,
Thank you for replying. You were right: I did find some information in the FSMC Application Note AN2784. Here's what I found:
The FSMC has up to 26 address lines, up to 4 chip selects and up to 16 data bits for each of the four supported types of memory. I'm only interested in SRAM for the purposes of this question.
Now I'm back to my original question: Does this mean that I would be able to address up to four pieces of a 64 M x 16 bit SRAM for a total of 512 M bytes with the FSMC? Or does it mean that I may only divide up the (2^26) 64 M word space up into as many as four sections, for an upper limit of 128 M bytes total?
If the Application Note (or any other ST documentation) spells it out for me, I seem to be missing it. I admit that I haven't read all the datasheets all the way through.
I'm asking for an answer in the form of a single number.
Thanks,
Dale Wheat
dalewheat.com
