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STM32 Family Wish List

stephen4
Associate II
Posted on July 18, 2009 at 14:02

STM32 Family Wish List

4 REPLIES 4
stephen4
Associate II
Posted on May 17, 2011 at 13:16

Since we have been discussing road maps for the STM32, I thought I would put in my opinion of what should be added/changed. I have been using the STM32F103 devices now for about 6 months and really enjoy working with this CPU. ST has done an amazing job with the Cortex core.

My wish list is short, only 4 items. I am sure others will add their wish list items as well.

32-bit timers. I am constantly cascading the 16-bit timers to make 32-bit timers. It would just be nicer if the timers had the same functionality, but with a 32 bit timer core.

DMA Engine. I would like to see an improved circular buffer management feature added to the DMA engine. Something similar to how a programmer would manage a circular buffer in software. The addition of read and write pointers in the circular buffer would go a long way to improve using the DMA as a FIFO manager for a USART in random length serial communication situations.

RTC Sub-second interrupts. The RTC can wake-up the core on a 1 second interval. It would be nice if the RTC could be used to wake up the core at a faster rate. If I want to put the core into deep sleep mode (turning off the clock), but need to wake the CPU in X milliseconds, then I need to implement an external timer to generate the wake-up call. The RTC running on its own clock could do this function if it could generate a sub-second wake-up pulse.

Improve the Documentation. The Reference Manual and Data Sheet are good but not great. I constantly struggle to understand how a peripheral function works. Please strive to provide great documentation.

kutnickg
Associate II
Posted on May 17, 2011 at 13:16

It's possible to get a DMA pointer by reading the DMA_CNDTRx register. If you take transfer_size - DMA_CNDTRx you can get the offset from the beginning of the array, which is what I think you want. However, you should be careful when dealing with situations where DMA_CNDTRx == transfer_size. If you implement a FIFO by blocking when read_pointer == write_pointer then you'll also want to check that DMA_CNDTRx != transfer_size. This only happens momentarily inbetween circular queue reloads.

At the very least this can allow you to implement a FIFO where the DMA is reading from a peripheral and writing to memory, since you would be the reader and can control the blocking in software. It's trickier where the DMA is reading from memory and writing to a peripheral because it won't know to block when the FIFO is empty. Here you might be better off buffering to fixed block sizes, perhaps with smaller block sizes allowed to flush the buffer.

I haven't used RTC, but from the documentation it would appear that you can choose periods below 1 second by setting the prescaler to the appropriate value. If RTCCLK is sourced with a 32.768KHz oscillator then it should be capable of operating at frequencies this high.

32bit timers would be nice.

[ This message was edited by: kutnickg on 06-07-2009 22:47 ]

halherta
Associate II
Posted on May 17, 2011 at 13:16

Quote:

Improve the Documentation. The Reference Manual and Data Sheet are good but not great. I constantly struggle to understand how a peripheral function works. Please strive to provide great documentation.

It would also be nice if ST organizes 2-3 training events in the Major Cities in N.America (including either Toronto or Montreal as i live in Canada). This would go a long way to reinforce the material in the guides/datasheets......for those living in N.America that is.

disirio
Associate II
Posted on May 17, 2011 at 13:16

I also think that 32 bit timers would be a good idea. Something with a 32 bit prescaler, 32 bit up counter and a series of comparators.

It would be really useful for high resolution timings.

Another improvement would be to add bit toggling capability to the GPIO BSRR registers. Currently, according to the reference manual, the combination BRy=BSy=1 sets the output pad, this combination could be assigned to a bit toggling mode (the combinations would work similarly to a JK flip flop).

The GPIO is already a very good cell, just the atomic bit toggling is missing.

Giovanni

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