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General Purpose Timer questions..

alex8
Associate II
Posted on August 24, 2009 at 16:01

General Purpose Timer questions..

4 REPLIES 4
alex8
Associate II
Posted on May 17, 2011 at 13:21

Hi,

I'm using TIM3, with TIM3 CH2 set up in Capture, and TIM3 CH2 set up for compare, both generating interrupts.

In the interrupt handler for T3, I determine the source by looking at the TIM3_SR:

Code:

<BR>if(*TIM3_SR & TIM_IT_CC2) { //we had a ZC capture event <BR> *TIM3_SR &= (u16)~TIM_IT_CC2; //clear flag in status <BR>..... calculate period between external events on CC2 input pin. ... <BR>return; <BR>} <BR> <BR>if (*TIM3_SR & TIM_IT_CC3) { //scheduler event (compare match) <BR> *TIM3_SR &= (u16)~TIM_IT_CC3; <BR>... do the scheduled action... <BR>return; <BR>} <BR> <BR>

I'm getting weird behavior: TIM3_SR bits getting set for CC4 and CC1, even though the TIM3_DIER has them disabled! Sometimes it looks like I even get an update event interrupt!

I suspect I'm going to realize I've done something really dumb, but I've got a few general questions that I haven't been able to dig the answer out of RM0008:

1. Do compare matching channels set bits in the TIMx_SR, even if their interrupt is not enabled?

2. with *TIM3_DIER = (TIM_IT_CC2 | TIM_IT_CC3) , is there anything other than chan2 and chan3 that can cause a TIM3 interrupt???

3. Is it safe to use a single timer, with some channels doing compares, and some channels doing captures?

4. What happens if I get a capture event on chan 2 simultaneous or close in time to a compare event on chan 3? Does the interrupt get requested for both events if I only clear one status bit? Am I in danger of getting both status bits set in the SR at the same time?

Is there a description of the timers somewhere other than RM0008?

regards,

Alex

[ This message was edited by: alex4 on 21-08-2009 08:30 ]

guyvo67
Associate II
Posted on May 17, 2011 at 13:21

Alex,

I only have experience on using the compares within a timer window. I use 3 timers each using the 4 compares and I noticed no problems. Using this in a mixed fashion I don't know if this is a good thing to do. But what you can try is bringing your capture match to another timer and see what it brings. Be aware that you only have one global timer interrupt for each general purpose timer. TIM1 has different vectors depending on how your timer is set up you can use brk,up and capture vectors separately.

And yes the rm0008 is rather general on that kind of things. Perhaps you can take a look at the technical reference r2p0 it's a bit more in depth on registers and stuff.

cheers

Guy

[ This message was edited by: guyvo67 on 22-08-2009 20:59 ]

stevemelnikoff9
Associate II
Posted on May 17, 2011 at 13:21

1) Yes. As a general rule, interrupt flags are set whether or not the interrupt is enabled. Obviously, if that particular interrupt is not enabled, the status flag being set will not trigger the interrupt.

2) No, if those are the only interrupts enabled.

3) Yes, it should be.

4) Generally, enabled interrupts will continue to be triggered until their status bits are cleared. So in this case, if both status bits are set, and only one is cleared within the interrupt, when the processor exits the interrupt, it will immediately re-enter it.

alex8
Associate II
Posted on May 17, 2011 at 13:21

Thanks!!!

Alex